Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.

Abstract: An embodiment of this invention A NiO chip is provided. The NiO chip includes a substrate, a nickel oxide thin film on the substrate, and a bioprobe layer on the nickel oxide thin film. The nickel oxide thin film has a light transmittance of more than 60% and a nanostructure. The bioprobe layer includes a plurality of bioprobes modified by Histidine (His) or a His-tagged protein.

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

Abstract: A sensing structure includes a sensing unit, a periphery circuit, and a connecting circuit. The connecting circuit connecting the sensing unit and the periphery circuit includes a connecting pattern. In an embodiment, the connecting pattern has at least two line widths. The line width of a part of the connecting pattern connecting the periphery circuit is greater than the line width of a part of the connecting pattern connecting the sensing unit. In an embodiment, the connecting pattern includes a mesh pattern having at least two mesh densities. The mesh density of a part of the mesh pattern connecting the periphery circuit is greater than the mesh density of a part of the mesh pattern connecting the sensing unit. In an embodiment, the connecting circuit includes lines between and connecting a single sensing series of the sensing unit and a periphery wire of the periphery circuit.

Abstract: Disclosed is a sensing structure including a sensing unit, a periphery circuit, and a connecting circuit. The connecting circuit connecting the sensing unit and the periphery circuit includes a connecting pattern. In an embodiment, the connecting pattern has at least two line widths. The line width of a part of the connecting pattern connecting the periphery circuit is greater than the line width of a part of the connecting pattern connecting the sensing unit. In an embodiment, the connecting pattern includes a mesh pattern having at least two mesh densities. The mesh density of a part of the mesh pattern connecting the periphery circuit is greater than the mesh density of a part of the mesh pattern connecting the sensing unit. In an embodiment, the connecting circuit includes lines between and connecting a single sensing series of the sensing unit and a periphery wire of the periphery circuit.

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.

Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.

Abstract: Various circuit board interconnect conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is disclosed that includes forming a conductor post on a side of a circuit board. The conductor post includes an end projecting away from the side of the circuit board. A solder mask is applied to the side of the circuit board to cover the conductor post. A thickness of the solder mask is reduced so that a portion of the conductor post projects beyond the solder mask.