Patents by Inventor Yu-Ling Hsieh
Yu-Ling Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144890Abstract: A backlight control circuit for a surface light emitting device is provided. The backlight control circuit includes a driving circuit. The driving circuit is configured to generate a plurality of driving currents to drive the surface light emitting device such that a plurality of backlight blocks of the surface light emitting device generate a plurality of brightness values. The surface light emitting device is divided into a first backlight area and a second backlight area. The second backlight area is closer to an edge of the surface light emitting device than the first backlight area. A first driving current of the plurality of driving currents is utilized for driving the light source of the first backlight area. A second driving current of the plurality of driving currents is utilized for driving the light source of the second backlight area. The second driving current is greater than the first driving current.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Applicant: Radiant Opto-Electronics CorporationInventors: Li-Fei Wang, Yu-Lin Hsieh, Sheng-Kai Fang, Pei-Ling Kao
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Publication number: 20200400664Abstract: An embodiment of this invention A NiO chip is provided. The NiO chip includes a substrate, a nickel oxide thin film on the substrate, and a bioprobe layer on the nickel oxide thin film. The nickel oxide thin film has a light transmittance of more than 60% and a nanostructure. The bioprobe layer includes a plurality of bioprobes modified by Histidine (His) or a His-tagged protein.Type: ApplicationFiled: March 31, 2020Publication date: December 24, 2020Inventors: Bor-Ran Li, Yu-Ling Hsieh, Chien-Wei Chen, Wan-Hsuan Lin
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Publication number: 20180102296Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: Advanced Micro Device (Shanghai) Co., Ltd.Inventors: I-Tseng LEE, Yu-Ling HSIEH
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Patent number: 9870969Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.Type: GrantFiled: February 28, 2014Date of Patent: January 16, 2018Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.Inventors: I-Tseng Lee, Yu-Ling Hsieh
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Patent number: 9811222Abstract: A sensing structure includes a sensing unit, a periphery circuit, and a connecting circuit. The connecting circuit connecting the sensing unit and the periphery circuit includes a connecting pattern. In an embodiment, the connecting pattern has at least two line widths. The line width of a part of the connecting pattern connecting the periphery circuit is greater than the line width of a part of the connecting pattern connecting the sensing unit. In an embodiment, the connecting pattern includes a mesh pattern having at least two mesh densities. The mesh density of a part of the mesh pattern connecting the periphery circuit is greater than the mesh density of a part of the mesh pattern connecting the sensing unit. In an embodiment, the connecting circuit includes lines between and connecting a single sensing series of the sensing unit and a periphery wire of the periphery circuit.Type: GrantFiled: July 17, 2015Date of Patent: November 7, 2017Assignee: Industrial Technology Research InstituteInventors: Bao-Shun Yau, Sheng-Feng Chung, Su-Tsai Lu, Yu-Ling Hsieh, Cheng-Yi Shih, Shu-Yi Chang, Kuo-Hua Tseng, Heng-Tien Lin
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Publication number: 20160018348Abstract: Disclosed is a sensing structure including a sensing unit, a periphery circuit, and a connecting circuit. The connecting circuit connecting the sensing unit and the periphery circuit includes a connecting pattern. In an embodiment, the connecting pattern has at least two line widths. The line width of a part of the connecting pattern connecting the periphery circuit is greater than the line width of a part of the connecting pattern connecting the sensing unit. In an embodiment, the connecting pattern includes a mesh pattern having at least two mesh densities. The mesh density of a part of the mesh pattern connecting the periphery circuit is greater than the mesh density of a part of the mesh pattern connecting the sensing unit. In an embodiment, the connecting circuit includes lines between and connecting a single sensing series of the sensing unit and a periphery wire of the periphery circuit.Type: ApplicationFiled: July 17, 2015Publication date: January 21, 2016Inventors: Bao-Shun Yau, Sheng-Feng Chung, Su-Tsai Lu, Yu-Ling Hsieh, Cheng-Yi Shih, Shu-Yi Chang, Kuo-Hua Tseng, Heng-Tien Lin
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Publication number: 20140246223Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.Type: ApplicationFiled: February 28, 2014Publication date: September 4, 2014Applicant: Advanced Micro Devices (Shanghai) Co., Ltd.Inventors: I-Tseng Lee, Yu-Ling Hsieh
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Patent number: 8772083Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.Type: GrantFiled: September 10, 2011Date of Patent: July 8, 2014Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Andrew K W Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
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Publication number: 20130062786Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.Type: ApplicationFiled: September 10, 2011Publication date: March 14, 2013Inventors: Andrew KW Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
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Publication number: 20110299259Abstract: Various circuit board interconnect conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is disclosed that includes forming a conductor post on a side of a circuit board. The conductor post includes an end projecting away from the side of the circuit board. A solder mask is applied to the side of the circuit board to cover the conductor post. A thickness of the solder mask is reduced so that a portion of the conductor post projects beyond the solder mask.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Inventors: Yu-Ling Hsieh, I-Tseng Lee, Yi-Hsiu Liu, Jen-Yi Tsai, Cheng-hua Fan