Patents by Inventor Yu-Ling Ko
Yu-Ling Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240429313Abstract: A method includes etching a semiconductor region aside of a gate stack to form a recess, forming a dielectric layer at a bottom of the recess, selectively forming a first semiconductor layer at the bottom of the recess, and epitaxially growing a second semiconductor layer on the first semiconductor layer. A bottom surface of the first semiconductor layer forms an interface with a top surface of the dielectric layer, with the interface extending to opposing sides of the recess. The selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions. The second semiconductor layer is formed using a second deposition process under second process conditions. The second process conditions are different from the first process conditions.Type: ApplicationFiled: September 28, 2023Publication date: December 26, 2024Inventors: Yu-Cheng Shiau, Chung-Ting Ko, Ting-Hsiang Chang, Shu Ling Liao, Sung-En Lin, Tai-Chun Huang, Tze-Liang Lee
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Patent number: 12176465Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.Type: GrantFiled: April 20, 2023Date of Patent: December 24, 2024Assignee: EPISTAR CORPORATIONInventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
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Patent number: 12165873Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.Type: GrantFiled: May 9, 2022Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: En-Ping Lin, Yu-Ling Ko, I-Chung Wang, Yi-Jen Chen, Sheng-Kai Jou, Chih-Teng Liao
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Publication number: 20230290863Abstract: Multiple-patterning techniques described herein enable forming fin structures of a semiconductor device in a manner that enables decreased fin-to-fin spacing of the fin structures while providing precise control over etching depth of the fin structures. In some implementations, an etch operation is performed to form a pattern in one or more mask layers that is used to etch a substrate to form the fin structures. The etch operation includes an advanced pulsing technique, in which a high-frequency radio frequency (RF) source and a low-frequency RF source are pulsed. Pulsing the high-frequency RF source and the low-frequency RF source in the etch operation reduces consumption of a thickness of the one or more mask layers which increases the aspect ratio of the pattern. This enables deeper etching of the substrate when forming the fin structures, which reduces the likelihood of under etching.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Guo-Cheng LYU, Kun-Yu LIN, Yu-Ling KO, Chih-Teng LIAO
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Patent number: 11646232Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.Type: GrantFiled: January 29, 2021Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Yu Lin, Yu-Ling Ko, I-Chen Chen, Chih-Teng Liao, Yi-Jen Chen
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Publication number: 20230068794Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a material layer over a semiconductor substrate; forming a plurality of spacer masks over the material layer; patterning the material layer into a plurality of masks below the spacer masks, wherein patterning the material layer comprises an atomic layer etching (ALE) process; and etching the semiconductor substrate through the masks.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Yu LIN, Yu-Ling KO, Chih-Teng LIAO
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Publication number: 20220384273Abstract: A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Kun-Yu LIN, En-Ping LIN, Yu-Ling KO, Chih-Teng LIAO
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Publication number: 20220384266Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: Kun-Yu LIN, Yu-Ling KO, I-Chen CHEN, Chih-Teng LIAO, Yi-Jen CHEN
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Publication number: 20220270886Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.Type: ApplicationFiled: May 9, 2022Publication date: August 25, 2022Inventors: En-Ping LIN, Yu-Ling KO, I-Chung WANG, Yi-Jen CHEN, Sheng-Kai JOU, Chih-Teng LIAO
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Patent number: 11328931Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.Type: GrantFiled: February 12, 2021Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: En-Ping Lin, Yu-Ling Ko, I-Chung Wang, Yi-Jen Chen, Sheng-Kai Jou, Chih-Teng Liao
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Publication number: 20220052042Abstract: A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.Type: ApplicationFiled: January 26, 2021Publication date: February 17, 2022Inventors: Kun-Yu Lin, En-Ping Lin, Yu-Ling Ko, Chih-Teng Liao
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Publication number: 20210366777Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.Type: ApplicationFiled: January 29, 2021Publication date: November 25, 2021Inventors: Kun-Yu Lin, Yu-Ling KO, I-Chen CHEN, Chih-Teng LIAO, Yi-Jen CHEN
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Patent number: 7920757Abstract: The image data are coded with field DCT or frame DCT depending on the characteristics of the image data. However different coding types will result in different boundary marks of boundaries between adjacent blocks or adjacent macro blocks. Therefore the de-blocking of a boundary between two adjacent blocks or adjacent macro blocks should be performed according to the format of image data and the coding type of the adjacent blocks or adjacent macro blocks.Type: GrantFiled: August 27, 2007Date of Patent: April 5, 2011Assignee: Silicon Integrated Systems Corp.Inventors: Chien-Chih Chen, Yu-Ling Ko
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Publication number: 20090080517Abstract: A method for reducing blocking artifacts in a video stream comprises receiving a picture of the video stream, wherein the picture includes a plurality of macroblocks and each of the plurality of macroblock includes four blocks, determining blocks with quantization parameters greater than a first threshold value in the picture, checking if block boundaries of the blocks are sharp and are real edges of objects in the picture according to pixel value differences between two adjacent pixels respectively located at both sides of the block boundaries, selecting filtering strengths of a de-blocking operation according to the pixel value differences when the block boundaries are sharp and are not real edges of the objects in the picture, and performing the de-blocking operation for two adjacent blocks at both sides of the block boundaries.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Inventors: Yu-Ling Ko, Chien-Chih Chen
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Publication number: 20090060361Abstract: The image data are coded with field DCT or frame DCT depending on the characteristics of the image data. However different coding types will result in different boundary marks of boundaries between adjacent blocks or adjacent macro blocks. Therefore the de-blocking of a boundary between two adjacent blocks or adjacent macro blocks should be performed according to the format of image data and the coding type of the adjacent blocks or adjacent macro blocks.Type: ApplicationFiled: August 27, 2007Publication date: March 5, 2009Inventors: Chien-Chih Chen, Yu-Ling Ko
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Publication number: 20090046783Abstract: A method for decoding a picture of a video stream includes decoding the video stream by a video decoder for generating a plurality of macroblocks corresponding to the picture, macroblock information corresponding to the plurality of macroblocks, and picture information corresponding to the picture; storing the macroblock information and the picture information into a memory buffer; and determining whether the picture is needed to be performed a de-blocking process by the video decoder according to the macroblock information and the picture information stored in the memory buffer.Type: ApplicationFiled: August 14, 2007Publication date: February 19, 2009Inventors: Chien-Chih Chen, Yu-Ling Ko