Patents by Inventor Yu-Lun Liu
Yu-Lun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240133918Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.Type: ApplicationFiled: April 12, 2023Publication date: April 25, 2024Inventors: MAO-NAN CHANG, CHI-LUN LIU, HSUEH-LIANG CHOU, YI-SHAN WU, CHIAO-JUNG LIN, YU-HSUN HSUEH
-
Patent number: 11967096Abstract: A depth estimation from focus method and system includes receiving input image data containing focus information, generating an intermediate attention map by an AI model, normalizing the intermediate attention map into a depth attention map via a normalization function, and deriving expected depth values for the input image data containing focus information from the depth attention map. The AI model for depth estimation can be trained unsupervisedly without ground truth depth maps. The AI model of some embodiments is a shared network estimating a depth map and reconstructing an AiF image from a set of images with different focus positions.Type: GrantFiled: February 22, 2022Date of Patent: April 23, 2024Assignee: MEDIATEK INC.Inventors: Ren Wang, Yu-Lun Liu, Yu-Hao Huang, Ning-Hsu Wang
-
Publication number: 20240109803Abstract: The present invention provides a flexible glass and manufacturing method thereof. The flexible glass includes a first straight part and a second straight part on two opposite ends thereof, a recess formed between the first straight part and the second straight part, and a pre-bent curve connection part disposed corresponding to the recess. The first straight part and the second straight part are not arranged on the same plane. The flexible glass has a first lateral side and a second lateral side, and the recess sinks from the first lateral side toward the second lateral side. Therefore, the flexible glass is provided with a greater bendability.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: CHENFENG OPTRONICS CORPORATIONInventors: CHING-FANG WONG, YU-WEI LIU, WEI-LUN ZENG, KUAN-HUA LIAO
-
Publication number: 20240093364Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.Type: ApplicationFiled: November 21, 2022Publication date: March 21, 2024Applicant: MSSCORPS CO., LTD.Inventors: CHI-LUN LIU, JUNG-CHIN CHEN, BANG-HAO HUANG, YU-HAN CHEN, LIKO HSU
-
Publication number: 20240067746Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.Type: ApplicationFiled: February 28, 2023Publication date: February 29, 2024Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
-
Patent number: 11553657Abstract: A method for regulating plant architecture includes applying a composition containing ?-Aminobutyric acid (GABA), glutamic acid and choline chloride to a plant. The composition for regulating plant architecture is also provided.Type: GrantFiled: June 7, 2021Date of Patent: January 17, 2023Assignee: CH BIOTECH R&D CO., LTD.Inventors: Yu-Lun Liu, Cho-Chun Huang, Gui-Jun Li, Kai Xia
-
Publication number: 20220386546Abstract: A method for regulating plant architecture includes applying a composition containing ?-Aminobutyric acid (GABA), glutamic acid and choline chloride to a plant. The composition for regulating plant architecture is also provided.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Yu-Lun Liu, Cho-Chun Huang, Gui-Jun Li, Kai Xia
-
Publication number: 20220309696Abstract: A depth estimation from focus method and system includes receiving input image data containing focus information, generating an intermediate attention map by an AI model, normalizing the intermediate attention map into a depth attention map via a normalization function, and deriving expected depth values for the input image data containing focus information from the depth attention map. The AI model for depth estimation can be trained unsupervisedly without ground truth depth maps. The AI model of some embodiments is a shared network estimating a depth map and reconstructing an AiF image from a set of images with different focus positions.Type: ApplicationFiled: February 22, 2022Publication date: September 29, 2022Inventors: Ren WANG, Yu-Lun LIU, Yu-Hao HUANG, Ning-Hsu WANG
-
Publication number: 20210244852Abstract: The present application provides a composition of corneal implantation, comprising: a collagen film, and renal proximal tubule cells which attached to the collagen film. In addition, the present application further provides a use of the composition of corneal implantation for implanting a patient with damaged cornea endothelium cells and a preparation method of the composition of corneal implantation.Type: ApplicationFiled: November 26, 2020Publication date: August 12, 2021Inventors: I-JONG WANG, TAI-HORNG YOUNG, I-NI CHIANG, YU-LUN LIU, TING-YUN SHIUE
-
Patent number: 10515953Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.Type: GrantFiled: October 13, 2017Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
-
Patent number: 10110873Abstract: A backward depth mapping method for stereoscopic image synthesis includes: providing a first coordinate and a first depth value of a pixel of a virtual view in a stereoscopic image; calculating a second coordinate and a second depth value of a pixel of reference view, which is obtained by mapping the virtual view, based on the first coordinate and the first depth value of the pixel of the virtual view; calculating an error value corresponding to the first depth value based on the second coordinate and second depth value; and determining a third depth value of the pixel of the virtual view based on the error value. As a result, it is possible to avoid the virtual view producing a crack and the pixel of the background from appearing at the crack of the foreground.Type: GrantFiled: July 15, 2015Date of Patent: October 23, 2018Assignee: National Chiao Tung UniversityInventors: Yu-Lun Liu, Hsueh-Ming Hang, Wen-Hsiang Tsai
-
Publication number: 20180040617Abstract: Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.Type: ApplicationFiled: October 13, 2017Publication date: February 8, 2018Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
-
Patent number: 9793268Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: GrantFiled: January 24, 2014Date of Patent: October 17, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
-
Patent number: 9543161Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a flowable-material (FM) layer over a substrate. The substrate has a first region and a second region. A top surface of the FM layer in the first region is higher than a top surface of the FM layer in the second region. The method also includes forming a plurality of trenches in the FM layer in the first region and performing annealing process to reflow the FM layer, wherein the plurality of trenches are filled with the FM layer.Type: GrantFiled: February 10, 2016Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Hao Su, Yu-Lun Liu, Chi-Kang Chang, Shih-Chi Fu, Kuei-Shun Chen, Chloe Hsu
-
Patent number: 9466528Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.Type: GrantFiled: October 6, 2014Date of Patent: October 11, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei-Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
-
Publication number: 20160205375Abstract: The invention is a backward depth mapping method for stereoscopic image synthesis, which includes: providing a first coordinate and a first depth value of a pixel of a virtual view in a stereoscopic image; calculating a second coordinate and a second depth value of a pixel of reference view, which is obtained by mapping the virtual view, based on the first coordinate and the first depth value of the pixel of the virtual view; calculating an error value corresponding to the first depth value of the pixel of the virtual view based on the second coordinate and second depth value of the pixel of the reference view; determining a third depth value of the pixel of the virtual view based on the error value corresponding to the first depth value of the pixel of the virtual view. Thereby, the invention can avoid the virtual view from producing crack and the pixel of background from appearing at the crack of the foreground.Type: ApplicationFiled: July 15, 2015Publication date: July 14, 2016Inventors: Yu-Lun Liu, Hsueh-Ming Hang, Wen-Hsiang Tsai
-
Patent number: 9274414Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.Type: GrantFiled: December 3, 2014Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lun Liu, Chia-Chu Liu, Kuei-Shun Chen, Chung-Ming Wang, Chie-Chieh Lin
-
Publication number: 20150214226Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Hao SU, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
-
Patent number: 9026957Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.Type: GrantFiled: February 25, 2014Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
-
Publication number: 20150086910Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.Type: ApplicationFiled: December 3, 2014Publication date: March 26, 2015Inventors: Yu-Lun Liu, Chia-Chu Liu, Kuei-Shun Chen, Chung-Ming Wang, Chie-Chieh Lin