Patents by Inventor Yu-Lun Lu
Yu-Lun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088096Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes an upper electronic structure, an upper connection structure, a first metal layer, a lower electronic structure, a lower connection structure and a second metal layer. The first metal layer electrically connects the upper electronic structure to the upper connection structure. The second metal layer electrically connects the lower electronic structure to the lower connection structure. The upper connection structure and the lower connection structure are bonded together.Type: ApplicationFiled: February 2, 2023Publication date: March 14, 2024Inventors: Yu-Lun Lu, Kong-Beng Thei
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Publication number: 20230420392Abstract: Some implementations described herein provide techniques and apparatuses for a stacked-die structure including a first integrated circuit device over a second integrated circuit device, where an operating voltage of the first integrated circuit device is different relative to an operating voltage of the second integrated circuit device. The first integrated circuit device includes a first portion of a seal ring structure of the stacked-die structure. The first portion includes an interconnect structure that connects a backside redistribution layer of the first integrated circuit device with first metal layers of the first integrated circuit device. The seal ring structure including the interconnect structure eliminates the use of diodes and electrically isolates well structures of the first integrated circuit device to reduce leakage paths relative to a stacked-die structure having a seal ring structure including a diode within the stacked-die structure.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Yu-Lun LU, Tsung-Chieh TSAI, Kong-Beng THEI, Yu-Chang JONG
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Publication number: 20230246030Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventors: HUNG-SHU HUANG, JHIH-BIN CHEN, MING CHYI LIU, YU-CHANG JONG, CHIEN-CHIH CHOU, JHU-MIN SONG, YI-KAI CIOU, TSUNG-CHIEH TSAI, YU-LUN LU
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Patent number: 11626398Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.Type: GrantFiled: March 11, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ta-Wei Lin, Fu-Hsiung Yang, Ching-Hsun Hsu, Yu-Lun Lu, Li-Hsuan Yeh, Tsung-Chieh Tsai, Kong-Beng Thei
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Publication number: 20220293590Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: TA-WEI LIN, FU-HSIUNG YANG, CHING-HSUN HSU, YU-LUN LU, LI-HSUAN YEH, TSUNG-CHIEH TSAI, KONG-BENG THEI
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Publication number: 20220282196Abstract: A perfusion cell culture device includes a driving module and a plurality of cell culture modules. The driving module includes a driving source connecting opening and a chamber. The chamber and the driving source connecting opening are connected. Each of the culture modules includes a fluid channel, a first elastic element, two flow direction controlling units and a cell culture zone. The fluid channel is disposed above the chamber, the first elastic element is disposed between the fluid channel and the chamber, the two flow direction controlling units are respectively disposed on two ends of the fluid channel and connected to the fluid channel selectively, and the cell culture zone is connected to the two flow direction controlling units.Type: ApplicationFiled: June 22, 2021Publication date: September 8, 2022Inventors: Wei-Han Lai, Jen-Huang Huang, Yu-Lun Lu
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Patent number: 8923001Abstract: An electronic device includes a housing, a chip card received in the housing, and a chip card protecting cover assembly. The chip card protecting cover assembly includes a housing, a first magnet and a second magnet. The magnetic force between the first magnet and the second magnet drives the protecting cover to rotate relative to the housing, thereby covering or exposing the chip card.Type: GrantFiled: April 27, 2012Date of Patent: December 30, 2014Assignee: Chi Mei Communications Systems, Inc.Inventors: Yu-Lun Lu, Chueh-Chuan Chen, Kun-Ying Lin, Chih-Chun Tsai, Po-Wen Kuo, Chih-Yung Wu, Po-Ching Huang
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Publication number: 20140197521Abstract: A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage.Type: ApplicationFiled: January 16, 2013Publication date: July 17, 2014Applicant: ILI TECHNOLOGY CORPORATIONInventors: Wei-Yao LIN, Chung-Wei WANG, Yu-Lun LU, Kuo-Ko CHEN
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Patent number: 8779519Abstract: A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage.Type: GrantFiled: January 16, 2013Date of Patent: July 15, 2014Assignee: Ili Technology CorporationInventors: Wei-Yao Lin, Chung-Wei Wang, Yu-Lun Lu, Kuo-Ko Chen
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Publication number: 20130235511Abstract: An electronic device includes a housing, a chip card received in the housing, and a chip card protecting cover assembly. The chip card protecting cover assembly includes a housing, a first magnet and a second magnet. The magnetic force between the first magnet and the second magnet drives the protecting cover to rotate relative to the housing, thereby covering or exposing the chip card.Type: ApplicationFiled: April 27, 2012Publication date: September 12, 2013Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.Inventors: YU-LUN LU, CHUEH-CHUAN CHEN, KUN-YING LIN, CHIH-CHUN TSAI, PO-WEN KUO, CHIH-YUNG WU, PO-CHING HUANG
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Patent number: 8101970Abstract: A semiconductor device of the present invention comprises: a P type semiconductor substrate, an N-well, a first P+ diffusion region, a second P+ diffusion region, a Schottky diode, a first N+ diffusion region, a second N+ diffusion region, a third P+ diffusion region, a fourth P+ diffusion region, a first insulation layer, a second insulation layer, a first parasitic bipolar junction transistor (BJT), and a second parasitic BJT. The Schottky diode is coupled to an input signal. The first N+ diffusion region and the second N+ diffusion region are coupled to a voltage source, respectively. When a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted.Type: GrantFiled: August 12, 2009Date of Patent: January 24, 2012Assignee: ILI Technology Corp.Inventors: Jing-Chi Yu, Yu-Lun Lu
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Publication number: 20110006396Abstract: A semiconductor device of the present invention comprises: a P type semiconductor substrate, an N-well, a first P+ diffusion region, a second P+ diffusion region, a Schottky diode, a first N+ diffusion region, a second N+ diffusion region, a third P+ diffusion region, a fourth P+ diffusion region, a first insulation layer, a second insulation layer, a first parasitic bipolar junction transistor (BJT), and a second parasitic BJT. The Schottky diode is coupled to an input signal. The first N+ diffusion region and the second N+ diffusion region are coupled to a voltage source, respectively. When a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted.Type: ApplicationFiled: August 12, 2009Publication date: January 13, 2011Inventors: Jing-Chi Yu, Yu-Lun Lu
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Publication number: 20100208399Abstract: An electrostatic discharge protection circuit includes: an electrostatic protection device coupled between a first reference voltage terminal and a signal pad for protecting a circuit coupled to the signal pad; a bipolar junction transistor including an emitter terminal coupled to the signal pad, a collector terminal coupled to a second reference voltage terminal, and a base terminal coupled to the first reference voltage terminal, wherein the bipolar junction transistor is a parasitic bipolar junction transistor of the electrostatic protection device; and a clamping circuit coupled to the bipolar junction transistor for clamping a conductivity of the bipolar junction transistor according to a signal received at the signal pad.Type: ApplicationFiled: April 9, 2009Publication date: August 19, 2010Inventors: Jing-Chi Yu, Hsiao-Ling Chen, Yu-Lun Lu, Chang-Chih Hsieh
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Patent number: 7695294Abstract: An adjustable plug includes a main body, a connecting end, and an adjustable end sleeve. The adjustable end sleeve is slidably positioned on the main body. The connecting end protrudes from the main body. The connecting end extends through the adjustable end sleeve, and protrudes out of the adjustable end sleeve.Type: GrantFiled: December 29, 2008Date of Patent: April 13, 2010Assignee: Chi Mei Communication Systems, Inc.Inventor: Yu-Lun Lu
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Patent number: 7679932Abstract: A housing mechanism (100) includes a main body (60) and a shield/cap (70). The main body accommodates an inner interface and defines a port (63) therein. The port is configured for allowing an outer interface to be inserted into the main body and for thereby engaging the outer interface with the inner interface. The shield is located near the port and is selectably rotatably positionable between a first position, in which the shield covers the port, and a second position, in which the shield does not cover the port. The first position and the second position cooperate to form an angle therebetween.Type: GrantFiled: July 12, 2007Date of Patent: March 16, 2010Assignee: Chi Mei Communication Systems, Inc.Inventor: Yu-Lun Lu
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Publication number: 20100015840Abstract: An adjustable plug includes a main body, a connecting end, and an adjustable end sleeve. The adjustable end sleeve is slidably positioned on the main body. The connecting end protrudes from the main body. The connecting end extends through the adjustable end sleeve, and protrudes out of the adjustable end sleeve.Type: ApplicationFiled: December 29, 2008Publication date: January 21, 2010Applicant: Chi Mei Communication Systems, Inc.Inventor: YU-LUN LU
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Patent number: 7579107Abstract: A portable electronic device (100) includes a main body (10), a cover (20), and a battery (30). The cover has at least one claw (252), and the cover is mounted to the main body by the at least one claw. The battery has at least one protrusion (35). Each protrusion is configured for engaging with a corresponding claw in such a manner that when the battery is positioned in a “tool” mode (i.e., as opposed to a “use”/battery-power mode) is pressed towards the cover, a given protrusion pushes a respective claw away from the main body to allow the cover to be separated from the main body.Type: GrantFiled: July 12, 2007Date of Patent: August 25, 2009Assignee: Chi Mei Communication Systems, Inc.Inventor: Yu-Lun Lu
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Publication number: 20080192455Abstract: A housing mechanism (100) includes a main body (60) and a shield/cap (70). The main body accommodates an inner interface and defines a port (63) therein. The port is configured for allowing an outer interface to be inserted into the main body and for thereby engaging the outer interface with the inner interface. The shield is located near the port and is selectably rotatably positionable between a first position, in which the shield covers the port, and a second position, in which the shield does not cover the port. The first position and the second position cooperate to form an angle therebetween.Type: ApplicationFiled: July 12, 2007Publication date: August 14, 2008Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.Inventor: YU-LUN LU
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Publication number: 20080193829Abstract: A portable electronic device (100) includes a main body (10), a cover (20), and a battery (30). The cover has at least one claw (252), and the cover is mounted to the main body by the at least one claw. The battery has at least one protrusion (35). Each protrusion is configured for engaging with a corresponding claw in such a manner that when the battery is positioned in a “tool” mode (i.e., as opposed to a “use”/battery-power mode) is pressed towards the cover, a given protrusion pushes a respective claw away from the main body to allow the cover to be separated from the main body.Type: ApplicationFiled: July 12, 2007Publication date: August 14, 2008Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.Inventor: YU-LUN LU