Patents by Inventor Yu-Lun OU
Yu-Lun OU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230336177Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.Type: ApplicationFiled: June 12, 2023Publication date: October 19, 2023Inventors: Yu-Lun OU, Ji-Yung LIN, Yung-Chen CHIEN, Ruei-Wun SUN, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
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Patent number: 11677400Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.Type: GrantFiled: June 8, 2022Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
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Publication number: 20220321126Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.Type: ApplicationFiled: June 8, 2022Publication date: October 6, 2022Inventors: Yu-Lun OU, Ji-Yung LIN, Yung-Chen CHIEN, Ruei-Wun SUN, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
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Patent number: 11387818Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.Type: GrantFiled: July 12, 2021Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Patent number: 11362660Abstract: A circuit includes a level shifter circuit, an output circuit, an enable circuit, a first and a second feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to generate at least a first and a second signal responsive to at least the first enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, and configured to receive the first and the second signal. The enable circuit is configured to generate a second enable signal responsive to the first enable signal. The first feedback circuit is configured to receive the first enable signal, the second enable signal and the first feedback signal. The second feedback circuit is configured to receive the first enable signal, the second enable signal and the second feedback signal.Type: GrantFiled: May 17, 2021Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
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Publication number: 20210344330Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Publication number: 20210273640Abstract: A circuit includes a level shifter circuit, an output circuit, an enable circuit, a first and a second feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to generate at least a first and a second signal responsive to at least the first enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, and configured to receive the first and the second signal. The enable circuit is configured to generate a second enable signal responsive to the first enable signal. The first feedback circuit is configured to receive the first enable signal, the second enable signal and the first feedback signal. The second feedback circuit is configured to receive the first enable signal, the second enable signal and the second feedback signal.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Yu-Lun OU, Ji-Yung LIN, Yung-Chen CHIEN, Ruei-Wun SUN, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
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Patent number: 11063578Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.Type: GrantFiled: August 27, 2020Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20210200927Abstract: A system and method for transistor placement in a standard cell layout includes identifying a plurality of transistors in a circuit. A drain terminal of each of the plurality of transistors is connected to an output of the circuit. The system and method also include determining that a first transistor and a second transistor of the plurality of transistors satisfy a merging priority, combining an active region of the first transistor and the second transistor to form a mega transistor having a common active region, and replacing the first transistor and the second transistor in the standard cell layout of the circuit with the mega transistor. The common active region combines the active region of a first drain terminal of the first transistor and a second drain terminal of the second transistor.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Inventors: Cheok-Kei Lei, Chi-Lin Liu, Yu-Lun Ou, Chien-Hsing Li, Zhe-Wei Jiang, Hui-Zhong Zhuang
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Patent number: 11012073Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.Type: GrantFiled: July 22, 2020Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
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Publication number: 20200395924Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Publication number: 20200350916Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
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Patent number: 10778197Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage is configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.Type: GrantFiled: November 16, 2019Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Patent number: 10735001Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.Type: GrantFiled: March 26, 2019Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
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Publication number: 20200083871Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage is configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.Type: ApplicationFiled: November 16, 2019Publication date: March 12, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 10483950Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.Type: GrantFiled: May 13, 2019Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20190319624Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.Type: ApplicationFiled: March 26, 2019Publication date: October 17, 2019Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
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Publication number: 20190280678Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.Type: ApplicationFiled: May 13, 2019Publication date: September 12, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 10291210Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.Type: GrantFiled: December 13, 2018Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20190115905Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.Type: ApplicationFiled: December 13, 2018Publication date: April 18, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH