Patents by Inventor Yu-Lung Hung
Yu-Lung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071822Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Lung CHUNG, Shin-Yi YANG, Yu-Chen CHAN, Han-Tang HUNG, Shu-Wei LI, Ming-Han LEE
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Patent number: 11290011Abstract: A power conversion apparatus includes: a power supply circuit, a load switch and a control circuit. The power supply circuit generates a first power. The load switch controls the power path from the power supply circuit to a load. The control circuit generates a switching control signal to control a conduction level of the load switch according to an enable signal. The control circuit controls a level of the switching control signal to soft start from a first level to a second level. During the soft start period, the switching control signal has plural waveform segments including a first waveform segment and a second waveform segment. A level variation speed of the first waveform segment is higher than a level variation speed of the second waveform segment. The first waveform segment level precedes the second waveform segment level.Type: GrantFiled: May 26, 2020Date of Patent: March 29, 2022Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Yu-Lung Hung, Hsing-Shen Huang
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Publication number: 20210126529Abstract: A power conversion apparatus includes: a power supply circuit, a load switch and a control circuit. The power supply circuit generates a first power. The load switch controls the power path from the power supply circuit to a load. The control circuit generates a switching control signal to control a conduction level of the load switch according to an enable signal. The control circuit controls a level of the switching control signal to soft start from a first level to a second level. During the soft start period, the switching control signal has plural waveform segments including a first waveform segment and a second waveform segment. A level variation speed of the first waveform segment is higher than a level variation speed of the second waveform segment. The first waveform segment level precedes the second waveform segment level.Type: ApplicationFiled: May 26, 2020Publication date: April 29, 2021Inventors: Yu-Lung Hung, Hsing-Shen Huang
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Patent number: 10964123Abstract: An insole design method and an insole design system are provided, and the method includes: capturing an uncompressed free foot model by a depth camera and obtaining a free foot model three-dimensional image; capturing a pressed foot model stepped on a transparent pedal by the depth camera and obtaining a pressed foot model three-dimensional image; aligning the free foot model three-dimensional image with the pressed foot model three-dimensional image; calculating and obtaining a plantar deformation quantity according to the aligned free foot model three-dimensional image and the aligned pressed foot model three-dimensional image; and completing the designed insole according to a sole projection plane or a three-dimensional profile of the specific sole and the plantar deformation quantity.Type: GrantFiled: August 14, 2019Date of Patent: March 30, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Lung Hung, Po-Fu Yen, Zhong-Yi Haung, Kang Chou Lin, Shang-Yi Lin, Chia-Chen Chen
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Publication number: 20200168004Abstract: An insole design method and an insole design system are provided, and the method includes: capturing an uncompressed free foot model by a depth camera and obtaining a free foot model three-dimensional image; capturing a pressed foot model stepped on a transparent pedal by the depth camera and obtaining a pressed foot model three-dimensional image; aligning the free foot model three-dimensional image with the pressed foot model three-dimensional image; calculating and obtaining a plantar deformation quantity according to the aligned free foot model three-dimensional image and the aligned pressed foot model three-dimensional image; and completing the designed insole according to a sole projection plane or a three-dimensional profile of the specific sole and the plantar deformation quantity.Type: ApplicationFiled: August 14, 2019Publication date: May 28, 2020Inventors: Yu-Lung HUNG, Po-Fu YEN, Zhong-Yi HAUNG, Kang Chou LIN, Shang-Yi LIN, Chia-Chen CHEN
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Publication number: 20160209681Abstract: This disclosure provides devices, systems, and methods for reducing substrate warpage in a display device. In one aspect, the display device includes a device substrate and a cover substrate, where the device substrate includes one or more display elements and the cover substrate includes a device cavity extending partially through the cover substrate. At least one of the display elements may be sealed by a primary seal in contact with and between the cover substrate and the device substrate to define a device area. A dummy area outside of the device area may be defined between the primary seal and a secondary seal, where the secondary seal is also in contact with and between the cover substrate and the device substrate. The display device may further include a dummy cavity extending partially through the cover substrate in the dummy area.Type: ApplicationFiled: January 16, 2015Publication date: July 21, 2016Inventors: Yu-Lung Hung, Hsuan Han Wang, Ming-Fa Chen
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Patent number: 7924209Abstract: A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced.Type: GrantFiled: June 5, 2009Date of Patent: April 12, 2011Assignee: Prolific Technology Inc.Inventors: Kuo-Jen Kuo, Kang-Shou Chang, Yu-Lung Hung
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Patent number: 7906952Abstract: A voltage regulator includes a comparator, a first voltage output unit, a second voltage output unit, a third voltage output unit, a first switch and a second switch. The voltage regulator receives an operating voltage and a reference voltage generated by a reference voltage generator, and then outputs a corresponding output voltage. The voltage regulator of the present invention can provide an operation mode, a suspend mode and a standby mode and can be switched among these modes to provide corresponding current driving capacity for respective operation states. When in the operation mode, the voltage regulator can supply a great current. When in the suspend mode, the voltage regulator consumes less power. When in the standby mode, the voltage regulator consumes even less power.Type: GrantFiled: March 10, 2009Date of Patent: March 15, 2011Assignee: Prolific Technology Inc.Inventors: Kuo-Jen Kuo, Yu-Lung Hung, Kang-Shou Chang
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Publication number: 20100201552Abstract: A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced.Type: ApplicationFiled: June 5, 2009Publication date: August 12, 2010Applicant: PROLIFIC TECHNOLOGY INC.Inventors: Kuo-Jen Kuo, Kang-Shou Chang, Yu-Lung Hung
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Patent number: 7772921Abstract: A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal.Type: GrantFiled: January 21, 2009Date of Patent: August 10, 2010Assignee: Prolific Technology Inc.Inventors: Yu-Lung Hung, Kang-Shou Chang
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Publication number: 20100176775Abstract: A voltage regulator includes a comparator, a first voltage output unit, a second voltage output unit, a third voltage output unit, a first switch and a second switch. The voltage regulator receives an operating voltage and a reference voltage generated by a reference voltage generator, and then outputs a corresponding output voltage. The voltage regulator of the present invention can provide an operation mode, a suspend mode and a standby mode and can be switched among these modes to provide corresponding current driving capacity for respective operation states. When in the operation mode, the voltage regulator can supply a great current. When in the suspend mode, the voltage regulator consumes less power. When in the standby mode, the voltage regulator consumes even less power.Type: ApplicationFiled: March 10, 2009Publication date: July 15, 2010Applicant: PROLIFIC TECHNOLOGY INC.Inventors: Kuo-Jen Kuo, Yu-Lung Hung, Kang-Shou Chang
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Publication number: 20090189645Abstract: A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal.Type: ApplicationFiled: January 21, 2009Publication date: July 30, 2009Applicant: Prolific Technology Inc.Inventors: Yu-Lung Hung, Kang-Shou Chang