Abstract: A voltage comparator includes an input portion, an output portion, and a diverting portion. The input portion accepts a first voltage and a second voltage and then outputs a first current based on the first voltage and outputs a second current based on the second voltage. The output portion outputs a result signal based on a difference between the first current and the second current. The diverting portion is electrically connected to the input portion and diverts a portion of the higher current amongst the first current and the second current.

Abstract: An output buffer including a first switch circuit and a buffer is provided. The first switch circuit receives first and second input signals. The buffer circuit includes first and second input stages, first and second output stages and a second switch circuit. The first and the second input stages are coupled to the first switch circuit. The first and the second output stages are coupled to the second switch circuit. The second switch circuit, coupled to the first and the second input stages and the first and the second output stages, selectively couples one of first and the second input stages to the first output stage and selectively couples the other to the second output stage. The first switch circuit further selectively provides one of the first and the second input signals to the first input stage and selectively provides the other to the second input stage.

Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.

Abstract: The invention discloses a driving apparatus for driving an LCD. The driving apparatus comprises a voltage control unit, an operating unit, a resistance unit, and a voltage selection unit. The operating unit comprises two sets of buffers formed by a plurality of operational amplifiers in negative feedback circuit. The two sets of buffers selectively receive positive polarity voltages and negative polarity voltages respectively. The voltage selection unit is provided with the positive polarity voltages and negative polarity voltages through the operating unit and the resistance unit. The voltage selection unit selectively provides the pixels of the LCD with the positive polarity voltage and the negative polarity voltage. Accordingly, each of the pixels is provided either with the positive polarity voltages or the negative polarity voltages by one of the two sets of buffers.

Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Abstract: The present invention discloses a process for the preparation of zirconium tungstate (ZrW2O8) ceramic body, comprising a reactive sintering step to react and sinter powders of the raw materials comprising a Zr-containing compound and a W-containing compound to form a zirconium tungstate ceramic body. The addition of zirconium tungstate powders as the seeds in the process can effectively reduce the steps, shorten the preparation time, lower the sintering temperature and duration, save the cost, and provide the zirconium tungstate ceramic body with uniform microstructure. Also, a process for the preparation of modified zirconium tungstate ceramic body is disclosed, by forming a second phase in the zirconium tungstate ceramic body to tune the thermal expansion coefficient of the zirconium tungstate ceramic body. The present invention also relates to the use of the modified zirconium tungstate ceramic body to provide a temperature compensated fiber bragg grating (FBG) device.

Abstract: An optical spectral coding scheme for fiber-optic code-division multiple-access (FO-CDMA) networks. The spectral coding is based on the pseudo-orthogonality of FO-CDMA codes properly written in the fiber Bragg grating (FBG) devices. For an incoming broadband optical signal, the designed Bragg wavelengths of the FBG will be reflected and spectrally coded with the written FO-CDMA address codes. Maximal-length sequence codes (M-sequence codes) are chosen as the signature or address codes to exemplify the coding and correlation processes in the FO-CDMA system. By assigning the N cyclic shifts of an M-sequence code vector to N users, the invention achieves an FO-CDMA network that can support N simultaneous users. The FO-CDMA encoding/decoding devices consist of a series of FBGs. To overcome the impact of multiple-access interference (MAI) on the performance of the FO-CDMA system, the FBG decoder is configured on the basis of orthogonal correlation functions of the nearly orthogonal M-sequence codes.

Abstract: The present invention discloses a process for the preparation of zirconium tungstate (ZrW2O8) ceramic body, comprising a reactive sintering step to react and sinter powders of the raw materials comprising a Zr-containing compound and a W-containing compound to form a zirconium tungstate ceramic body. The addition of zirconium tungstate powders as the seeds in the process can effectively reduce the steps, shorten the preparation time, lower the sintering temperature and duration, save the cost, and provide the zirconium tungstate ceramic body with uniform microstructure. Also, a process for the preparation of modified zirconium tungstate ceramic body is disclosed, by forming a second phase in the zirconium tungstate ceramic body to tune the thermal expansion coefficient of the zirconium tungstate ceramic body. The present invention also relates to the use of the modified zirconium tungstate ceramic body to provide a temperature compensated fiber bragg grating (FBG) device.

Abstract: An optical spectral coding scheme for fiber-optic code-division multiple-access (FO-CDMA) networks. The spectral coding is based on the pseudo-orthogonality of FO-CDMA codes properly written in the fiber Bragg grating (FBG) devices. For an incoming broadband optical signal, the designed Bragg wavelengths of the FBG will be reflected and spectrally coded with the written FO-CDMA address codes. Maximal-length sequence codes (M-sequence codes) are chosen as the signature or address codes to exemplify the coding and correlation processes in the FO-CDMA system. By assigning the N cyclic shifts of an M-sequence code vector to N users, the invention achieves an FO-CDMA network that can support N simultaneous users. The FO-CDMA encoding/decoding devices consist of a series of FBGs. To overcome the impact of multiple-access interference (MAI) on the performance of the FO-CDMA system, the FBG decoder is configured on the basis of orthogonal correlation functions of the nearly orthogonal M-sequence codes.

Abstract: This invention discloses a plurality of compensating devices for correcting temperature deviation of optical fiber Bragg grating (FBG). These devices includes means for compressing optical fibers being affixed to a substrate, and fiber grids being cured to the substrate and/or the compressing means under a thermal state, or fiber grids being affixed to the substrate and/or the compressing means while the fiber grids are under tension. This invention further discloses methods for manufacturing such devices. The FBG thermal compensating devices according to this invention consist the advantages of simple constructions and simplified manufacturing processes. One of the devices can resolve the heat-dissipating problem so as to allow immediate thermal expansion of the fiber grids. Another device allows rapid positioning and manufacturing. One of the devices allows the fiber grids to be directly secured to a thermal compensating substrate without needing additional pre-processes.

Abstract: A method of linkage with springs mold is provided to simulate the condition of forces acting on a bonding wire for semiconductor package. The bonding wire profile can be formed by means of combining several sets of linkage with springs, wherein the coefficients of elasticity and plasticity of the springs are determined by the bending angle of two linkages which simulates the elastic-plastic deformation of the wires. The operational model can be simplified and the time can be saved by using the multiple degrees of freedom of the links/springs to analyze the profile and forces on the fine wire. Necking and fracture during formation process of the bonding wire can be avoided by the present method and design to achieve the optimum design for wire bonding profiles.