Abstract: The present disclosure relates to the field of display technologies, and discloses a display panel, a preparation method thereof, and a display device; the display panel has a display area and a non-display area adjacent to the display area, and the display panel includes an array substrate, an opposite substrate, and a retaining wall structure; a bonding electrode is arranged on the array substrate, and located in the non-display area; the opposite substrate and the array substrate are arranged opposite to each other; the retaining wall structure is arranged on the side of the array substrate close to the opposite substrate, and at least part of the retaining wall structure is located between the display area and the bonding electrode.

Abstract: The disclosure provides an array substrate and a touch display device. The array substrate includes a display area and a non-display area, and the non-display area includes a fan-out area and a signal input area. The display area is provided with a plurality of display data lines and a plurality of touch data lines, the fan-out area is provided with a plurality of display data fan-out lines and a plurality of touch data fan-out lines, the fan-out area includes a first part and a second part which are adjacently distributed in a direction from the display area to the signal input area.

Abstract: A display panel and a display device are provided, and relate to the field of displaying. The display panel includes a display area and a peripheral area located at a periphery of the display area. The peripheral area includes a package region and an UDC region located between the display area and the package region. The display panel further includes a transition area surrounding the UDC region, and an opposite substrate and an array substrate arranged opposite to each other. In the UDC region, the opposite substrate and the array substrate are both light-transmissible areas; in the transition area, at least one spacer ring surrounding the UDC region is arranged on the opposite substrate, and each spacer ring includes a plurality of spacers that are spaced apart from each other. The technical solutions of the present disclosure can implement UDCs for the medium-sized display product and the large-sized display product.

Abstract: An array substrate includes: a base substrate, a light shielding layer on a first surface of the base substrate, and a plurality of pixel units and a first common electrode bus on a second surface of the base substrate. The base substrate includes a display region, first and second peripheral regions. Orthographic projections of the pixel units on the base substrate are arranged in an array in the display region. At least part of an orthographic projection of the light shielding layer and at least part of an orthographic projection of the first common electrode bus on the base substrate are in the second peripheral region, and the first common electrode bus is electrically connected to the common electrode included in at least one pixel unit. A distribution density of the first common electrode bus in the first peripheral region is smaller than that in the second peripheral region.

Abstract: The present disclosure relates to an array substrate, a display panel, and an electronic device. The array substrate includes a plurality of sub-pixel regions, a gate line layer, and a common electrode layer. Each sub-pixel region of the sub-pixel regions has two sub-pixel units disposed in a same row and two thin film transistors connected to the two sub-pixel units respectively. The gate line layer has gate lines and gate electrodes. Control electrodes of two thin film transistors of each sub-pixel region are respectively connected to two gate lines located on two ends of the sub-pixel region through corresponding gate electrodes.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, the base substrate includes an IC region, and the IC region includes a first electrode arrangement region and a first transistor arrangement region. The display substrate includes a plurality of first touch electrodes arranged in rows and columns in the first electrode arrangement region, and a plurality of first switching transistors arranged in the first transistor arrangement region. Each first touch electrode is electrically coupled to a corresponding first switching transistor, and an orthogonal projection of a display data receiving electrode onto the base substrate does not overlap with an orthogonal projection of the first touch electrode onto the base substrate.

Abstract: The present application provides a carbonaceous material and a preparation method therefor, and a secondary battery and an electrical device comprising the same. The carbonaceous material has 0.13?A/B?0.50, wherein A represents a mass of water vapor adsorbed on the carbonaceous material after a water vapor adsorption test by placing the carbonaceous material under constant temperature and humidity conditions of 25° C. and 100% RH for 100 h, and B represents an initial mass of the carbonaceous material. The present application can simultaneously improve the capacity and initial coulombic efficiency of the carbonaceous material.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: An array substrate, a manufacturing method and a display device. The array substrate includes: a base substrate; a plurality of gate lines and a plurality of data lines; a plurality of touch signal lines; a plurality of touch electrodes; a plurality of pixel electrodes; and an insulation layer. The touch signal line and a transparent conductive layer where the pixel electrode is located are arranged at a side of the insulation layer away from a transparent conductive layer where the touch electrode is located, an orthogonal projection of the pixel electrode onto the base substrate is separated from an orthogonal projection of the touch signal line onto the base substrate to be insulated from each other, and each touch electrode is coupled to at least one touch signal line through a via hole in the insulation layer.

Abstract: Systems and methods described herein relate to automatic index recommendations for improved database query performance. Candidate indexes are identified. The candidate indexes are associated with a database query that is classified as a slow query. A feature vector is generated for each candidate index to represent statement features and statistical features associated with the candidate index. The feature vectors are provided to one or more machine learning models to obtain an index recommendation value for each candidate index. An index recommendation is presented at a user device. The index recommendation identifies a first index of the candidate indexes based at least partially on the index recommendation value obtained for the first index. User input indicative of a user selection of the first index is received. A database schema is updated to include the first index in response to the user input.

Abstract: An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.

Abstract: A carbonaceous material contains element O, where the content of element O of the carbonaceous material tested by X-ray photoelectron spectroscopy is denoted as A, the content of element O of the carbonaceous material tested by elemental analysis is denoted as B, and the carbonaceous material satisfies A/B?3 and 5 wt %?A?20 wt %.

Abstract: A carbonaceous material has an adsorption velocity v that satisfies 0.015?v?0.050 when subjected to an adsorption test using water vapor at a constant temperature and humidity of 25° C. and 40% RH. The water vapor adsorption test is performed under the following conditions: in a constant temperature and humidity chamber at 25° C. and 40% RH, the carbonaceous material with a mass of m1 is placed in a container, and a water vapor adsorption mass m2 and a water vapor adsorption time t are recorded when the water vapor adsorption of the carbonaceous material reaches equilibrium, and the water vapor adsorption velocity is v=m2/(m1×t), where mi is measured in g, m2 is measured in g, and t is measured in h.

Abstract: A carbonaceous material where in the CO2 adsorption test of the carbonaceous material, the total CO2 adsorption at 0° C. and a relative pressure P/P0 between 10?8 and 0.029 is recorded as A, the adsorption time is recorded as B, and the carbonaceous material satisfies: A/B?1.7 cm3/(g×h) STP, where STP is the standard condition, P represents the test pressure of CO2, and P0 represents the saturated vapor pressure of CO2 at 0° C.

Abstract: Provided is a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, and a black matrix; wherein each the sub-pixel is divided into at least two domains along a column direction of the array; and the data line deviates from the column direction of the array and bends toward the row direction of the array to form a corner, wherein a distance between an outer edge of an orthographic projection of the black matrix covering the corner onto the substrate and an outer edge of an orthographic projection of the corner onto the substrate is greater than a distance between an edge of an orthographic projection of the black matrix covering rest of the data line onto the substrate and a corresponding edge of an orthographic projection of the data line covered by the black matrix onto the substrate.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: a plurality of gate lines extending in a first direction, and a plurality of data lines extending in a second direction and crossing the gate lines to define a plurality of sub-pixels; a plurality of touch signal lines extending in the second direction and arranged in light shielding regions of the sub-pixels; a plurality of touch electrodes insulated from each other; and a plurality of metal pattern units corresponding to the sub-pixels respectively and arranged in the light shielding region of each sub-pixel. The metal pattern unit includes a first metal strip arranged on at least one side of the data line and extending in the second direction.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain epitaxial feature disposed over a substrate, and the source/drain epitaxial feature includes about 0.002 atomic percent to about 0.02 atomic percent of aluminum. The structure further includes a first semiconductor layer in contact with the source/drain epitaxial feature and a gate electrode layer disposed over the first semiconductor layer.

Abstract: The present disclosure relates to the field of display technologies, and discloses a display panel, a preparation method thereof, and a display device; the display panel has a display area and a non-display area adjacent to the display area, and the display panel includes an array substrate, an opposite substrate, and a first alignment film and a retaining wall structure; a bonding electrode is arranged on the array substrate, and located in the non-display area; the opposite substrate and the array substrate are arranged opposite to each other; the first alignment film is arranged on a side of the array substrate close to the opposite substrate; the retaining wall structure is arranged on the side of the array substrate close to the opposite substrate, and at least part of the retaining wall structure is located between the first alignment film and the bonding electrode.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a touch control signal line disposed on the base substrate, and a pixel electrode disposed at a side of the touch control signal line away from the base substrate; the pixel electrode includes at least four strip electrodes, a slit is provided between adjacent strip electrodes of at least two of the strip electrodes, the slit at least includes a first corner end located on at least one end of the slit; the slit includes a first slit, a second slit and a third slit disposed between the first slit and second slit; an area of an orthographic projection of a first corner end of the third slit on the base substrate is greater than an area of an orthographic projection of a first corner end of the second slit on the base substrate.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.