Patents by Inventor Yu-Mei Hsu

Yu-Mei Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9126140
    Abstract: Embodiments of the present disclosure provide for collection devices, methods of making collection devices, methods of collecting gases and aerosol particles, and the like.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 8, 2015
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Chang-Yu Wu, Yu-Mei Hsu, Alex Theodore, Lin Shou, Danielle Lyon Hall
  • Patent number: 9084958
    Abstract: Embodiments of the present disclosure provide for collection devices, methods of making collection devices, methods of collecting gases and aerosol particles, and the like.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: July 21, 2015
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Chang-Yu Wu, Yu-Mei Hsu, Alex Theodore, Lin Shou, Danielle Lyon Hall
  • Publication number: 20130239808
    Abstract: Embodiments of the present disclosure provide for collection devices, methods of making collection devices, methods of collecting gases and aerosol particles, and the like.
    Type: Application
    Filed: April 1, 2013
    Publication date: September 19, 2013
    Applicant: University of Florida Research Foundation, Inc.
    Inventors: Chang-Yu Wu, Yu-Mei Hsu, Alex Theodore, Lin Shou, Danielle Lyon Hall
  • Publication number: 20130192463
    Abstract: Embodiments of the present disclosure provide for collection devices, methods of making collection devices, methods of collecting gases and aerosol particles, and the like.
    Type: Application
    Filed: October 17, 2011
    Publication date: August 1, 2013
    Inventors: Chang-Yu Wu, Yu-Mei Hsu, Alex Theodore, Lin Shou, Danielle Lyon Hall
  • Patent number: 8240029
    Abstract: A method for forming an isolated inner lead from a leadframe is revealed. The leadframe primarily comprises a plurality of leads, the isolated inner lead, and an external lead. Each lead has an inner portion having a finger. The isolated inner lead having two fingers is completely formed inside a molding area and is made of the same metal leadframe as the leads. One finger of the isolated inner lead and the fingers of the leads are linearly arranged. The other finger of the isolated inner lead is adjacent to a finger of the external lead. At least one of the inner portions divides the isolated inner lead from the external lead. The isolated inner lead is integrally connected to an adjacent one of the inner portions by a connecting block. A tape-attaching step is performed to mechanically connect the isolated inner lead where two insulating tapes are attached in a manner that the connecting block can be removed.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: August 14, 2012
    Assignee: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Patent number: 8049339
    Abstract: A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: November 1, 2011
    Assignee: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Patent number: 7821112
    Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.
    Type: Grant
    Filed: March 9, 2008
    Date of Patent: October 26, 2010
    Assignee: Powertech Technology Inc
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Patent number: 7812430
    Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed on a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as ā€œSā€ shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: October 12, 2010
    Assignee: Powertech Technology Inc.
    Inventors: Chin-Fa Wang, Wan-Jung Hsieh, Yu-Mei Hsu
  • Patent number: 7750444
    Abstract: A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: July 6, 2010
    Assignee: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20100127362
    Abstract: A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip.
    Type: Application
    Filed: November 24, 2008
    Publication date: May 27, 2010
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Wen-Jeng FAN, Yu-Mei HSU
  • Patent number: 7723828
    Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: May 25, 2010
    Assignee: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20100122454
    Abstract: A method for forming an isolated inner lead from a leadframe is revealed. The leadframe primarily comprises a plurality of leads, the isolated inner lead, and an external lead. Each lead has an inner portion having a finger. The isolated inner lead having two fingers is completely formed inside a molding area and is made of the same metal leadframe as the leads. One finger of the isolated inner lead and the fingers of the leads are linearly arranged. The other finger of the isolated inner lead is adjacent to a finger of the external lead. At least one of the inner portions divides the isolated inner lead from the external lead. The isolated inner lead is integrally connected to an adjacent one of the inner portions by a connecting block. A tape-attaching step is performed to mechanically connect the isolated inner lead where two insulating tapes are attached in a manner that the connecting block can be removed.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20090302443
    Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die- bonding plane under the chip is desirably prevented.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 10, 2009
    Inventors: Chin-Fa Wang, Wan-Jung Hsieh, Yu-Mei Hsu
  • Publication number: 20090283878
    Abstract: A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Wen-Jeng FAN, Yu-Mei HSU
  • Patent number: 7619307
    Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: November 17, 2009
    Assignee: Powertech Technology Inc.
    Inventors: Chin-Fa Wang, Wan-Jung Hsieh, Yu-Mei Hsu
  • Publication number: 20090224380
    Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed oil a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as ā€œSā€ shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: Chin-Fa WANG, Wan-Jung Hsieh, Yu-Mei Hsu
  • Publication number: 20090224377
    Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.
    Type: Application
    Filed: March 9, 2008
    Publication date: September 10, 2009
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20090160038
    Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.
    Type: Application
    Filed: February 8, 2008
    Publication date: June 25, 2009
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20050050195
    Abstract: The present invention discloses a control method for setting up the operation time of a wire connection device by installing a detection control software in a driver program, and the detection control software sets up the detection operation time of the wireless connection device such that when a computer device is turned on, the detection control software controls the ON/OFF time of the wireless connection device according to the setup of the detection operation time through the driver program to avoid unnecessary waste of electric power and any possible risk to pathological changes caused by exposing our body under the electromagnetic waves for a long time.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 3, 2005
    Applicant: INVENTEC CORPORATION
    Inventors: Chung-Hui Chen, Yu-Mei Hsu, Yu-Hua Hsu, Fu-Zen Hsieh
  • Patent number: D568607
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: May 13, 2008
    Inventor: Yu-Mei Hsu