Abstract: A decision feedback equalizer is disclosed. The decision feedback equalizer comprises an amplifier circuit and a latch. The amplifier circuit is configured to receive an input signal, a decision feedback signal and a control signal, and is configured to adjust its driving capability according to the decision feedback signal and the control signal to provide an amplified signal of the input signal. The latch is configured to latch the amplified signal as an output signal.

Abstract: A decision feedback equalizer is disclosed. The decision feedback equalizer comprises an amplifier circuit and a latch. The amplifier circuit is configured to receive an input signal, a decision feedback signal and a control signal, and is configured to adjust its driving capability according to the decision feedback signal and the control signal to provide an amplified signal of the input signal. The latch is configured to latch the amplified signal as an output signal.

Abstract: A multi-stage receiver comprises an input stage, an intermediate stage, and an output stage. The input stage is configured to provide a first signal and a second signal. The intermediate stage is coupled to the input stage and comprises a first amplifying circuit and a second amplifying circuit. Positive and negative input terminals of the first amplifying circuit receive the first signal and the second signal, respectively. Positive and negative input terminals of the second amplifying circuit receive the second signal and the first signal, respectively. The output stage is coupled to the intermediate stage and configured to generate low-skewed differential signals according to output signals of the intermediate stage.

Abstract: A multi-stage receiver comprises an input stage, an intermediate stage, and an output stage. The input stage is configured to provide a first signal and a second signal. The intermediate stage is coupled to the input stage and comprises a first amplifying circuit and a second amplifying circuit. Positive and negative input terminals of the first amplifying circuit receive the first signal and the second signal, respectively. Positive and negative input terminals of the second amplifying circuit receive the second signal and the first signal, respectively. The output stage is coupled to the intermediate stage and configured to generate low-skewed differential signals according to output signals of the intermediate stage.

Abstract: A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained.

Abstract: A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained.

Abstract: A block parallel efuse apparatus blown with serial data input. The block parallel apparatus includes a high voltage source, efuse circuits, a plurality of multiplex, registers, and an input-output terminal, wherein each efuse circuit includes an efuse, a blown-control terminal, an input terminal, and an output terminal. Each efuse is coupled between the high voltage source and the output terminal of the efuse circuit.

Abstract: A block parallel efuse apparatus blown with serial data input. The block parallel apparatus includes a high voltage source, efuse circuits, a plurality of multiplex, registers, and an input-output terminal, wherein each efuse circuit includes an efuse, a blown-control terminal, an input terminal, and an output terminal. Each efuse is coupled between the high voltage source and the output terminal of the efuse circuit.