Patents by Inventor YU-MIN CHOU

YU-MIN CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12051719
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer and a third nitride layer in sequence over the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and a second electrode in the second opening; removing the first sacrificial layer and the second sacrificial layer concurrently; and forming a conductive layer, conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer and the third nitride layer.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: July 30, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Min Chou, Shih-Fan Kuan
  • Patent number: 12021114
    Abstract: The present disclosure provides a semiconductor structure with a single side capacitor. The semiconductor structure includes a substrate having a first landing pad therein, and a first capacitor disposed over the substrate. The first capacitor includes: a first electrode, disposed over and extending vertically away from the first landing pad; a first dielectric layer, at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode, surrounding the first dielectric layer and the first electrode.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 25, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Min Chou, Shih-Fan Kuan
  • Publication number: 20230402501
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer and a third nitride layer in sequence over the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and a second electrode in the second opening; removing the first sacrificial layer and the second sacrificial layer concurrently; and forming a conductive layer, conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer and the third nitride layer.
    Type: Application
    Filed: May 19, 2022
    Publication date: December 14, 2023
    Inventors: YU-MIN CHOU, SHIH-FAN KUAN
  • Publication number: 20230378248
    Abstract: The present disclosure provides a semiconductor structure with a single side capacitor. The semiconductor structure includes a substrate having a first landing pad therein, and a first capacitor disposed over the substrate. The first capacitor includes: a first electrode, disposed over and extending vertically away from the first landing pad; a first dielectric layer, at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode, surrounding the first dielectric layer and the first electrode.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 23, 2023
    Inventors: YU-MIN CHOU, SHIH-FAN KUAN