Patents by Inventor Yu-Min Yeh

Yu-Min Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170269096
    Abstract: A reaction system comprises at least one additive and at least one reaction base-plane for augmenting chemical reaction, photoelectrochemical reaction, photochemical reaction or electrochemical reaction. The reaction system further comprises at least one reaction substrate carried out to the chemical reaction, the photoelectrochemical reaction, the photochemical reaction or the electrochemical reaction with the at least one additive and the at least one reaction base-plane. The at least one additive is a kind of reaction enhancer added in the reaction system to improve, augment or accumulate the effeteness of at least one reaction result.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 21, 2017
    Inventors: WEI-LUN HUANG, WU-CHOU SU, HAI-WEN CHEN, YU-MIN YEH, WEI-PANG CHUNG, TE-FU YEH, HSISHENG TENG, CHIAO-YI TENG, LIANG-CHE CHEN, CHUNG-JEN CHUNG
  • Patent number: 9000821
    Abstract: A delay circuit for receiving an input signal and generating a delayed output signal. The delay circuit includes a first delay module and a second delay module. The first delay module includes a first delay unit for generating a first delayed signal according to an input signal and a first logic unit, coupled to the first delay unit, for generating a first delayed output signal according to the first delayed signal and the input signal. The second delay module includes a second delay unit for generating a second delayed signal according to the first delayed output signal and a second logic unit, coupled to the second delay unit, for generating the delayed output signal according to the second delayed signal and the input signal.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 7, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Huimin Tsai, Yu-Min Yeh
  • Publication number: 20140111265
    Abstract: A delay circuit for receiving an input signal and generating a delayed output signal. The delay circuit includes a first delay module and a second delay module. The first delay module includes a first delay unit for generating a first delayed signal according to an input signal and a first logic unit, coupled to the first delay unit, for generating a first delayed output signal according to the first delayed signal and the input signal. The second delay module includes a second delay unit for generating a second delayed signal according to the first delayed output signal and a second logic unit, coupled to the second delay unit, for generating the delayed output signal according to the second delayed signal and the input signal.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 24, 2014
    Applicant: MStar Semiconductor, Inc.
    Inventors: Huimin Tsai, Yu-Min Yeh