Patents by Inventor Yu-Ming Cheng

Yu-Ming Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133736
    Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a control gate, an erase gate, and a floating gate. The select gate is disposed on the substrate. The control gate is disposed on the substrate and laterally spaced apart from the select gate. The erase gate is disposed on the substrate and laterally spaced apart from the control gate, and the erase gate includes a concave corner. The floating gate is covered with the control gate and the erase gate. The floating gate includes a convex corner which faces the concave corner of the erase gate, and the vertex of the floating gate is lower than a top surface of the select gate.
    Type: Application
    Filed: June 18, 2024
    Publication date: April 24, 2025
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai
  • Publication number: 20250133775
    Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a trench, an erase gate, a control gate, and a floating gate. The trench is disposed in the substrate. The erase gate is disposed in the trench and includes a concave corner. The control gate is disposed on the substrate, and a bottom surface of the control gate is higher than a bottom surface of the erase gate. The floating gate is disposed on the substrate, and the floating gate includes a lower tip pointing toward the concave corner of the erase gate and extending beyond a sidewall of the trench.
    Type: Application
    Filed: March 22, 2024
    Publication date: April 24, 2025
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai
  • Patent number: 12279422
    Abstract: A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 15, 2025
    Assignee: IOTMEMORY TECHNOLOGY INC.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Chen-Ming Tsai, Yu-Ming Cheng
  • Publication number: 20250120077
    Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Inventors: Der-Tsyr Fan, l-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai, l-Chun Chuang
  • Publication number: 20240304692
    Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a floating gate, a floating gate cap layer, and an erase gate. The select gate is disposed on the substrate. The floating gate is disposed on the substrate and laterally spaced apart from the select gate, where the floating gate includes top edges forming a closed shape as viewed from a top-down perspective. The floating gate cap layer is disposed on a top surface of the floating gate, where an area of a top surface of the floating gate cap layer is less than an area of a bottom surface of the floating gate. The erase gate is disposed on the floating gate, and one or more of the top edges are covered with the erase gate. A control gate is covered with the erase gate.
    Type: Application
    Filed: July 27, 2023
    Publication date: September 12, 2024
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng
  • Publication number: 20240274682
    Abstract: A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 15, 2024
    Applicant: IOTMEMORY TECHNOLOGY INC.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng
  • Publication number: 20240162316
    Abstract: A non-volatile memory device includes at least one memory cell and the memory cell includes a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate and laterally spaced apart from the select gate. The control gate comprises a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion disposed between the select gate and the control gate and includes a first top tip laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, where the horizontal portion includes a lateral tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.
    Type: Application
    Filed: October 6, 2023
    Publication date: May 16, 2024
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng
  • Publication number: 20240162315
    Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 16, 2024
    Applicant: IOTMEMORY TECHNOLOGY INC.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng
  • Publication number: 20240162317
    Abstract: A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)<(T1)<2(T2).
    Type: Application
    Filed: October 20, 2023
    Publication date: May 16, 2024
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai
  • Publication number: 20230232623
    Abstract: A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Applicant: IOTMEMORY TECHNOLOGY INC.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Chen-Ming Tsai, Yu-Ming Cheng
  • Publication number: 20200152646
    Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.
    Type: Application
    Filed: March 20, 2019
    Publication date: May 14, 2020
    Applicant: IoTMemory Technology Inc.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Yu-Ming Cheng
  • Patent number: 10650212
    Abstract: An optical identification method for sensing a physiological feature, includes: projecting light to a physiological portion for generating reflection light from the physiological portion; receiving the reflection light, to generate an image; generating slant pattern information according to the image; transforming the slant pattern information into a pattern identification matrix; and determining the physiological feature according to the pattern identification matrix.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 12, 2020
    Assignee: BEYOND TIME INVETMENTS LIMITED
    Inventors: Chu-Hsin Chang, Jun-Shian Hsiao, Ju-Yu Yu, Chun-Fu Lin, Yu-Ming Cheng, Hui-Min Tsai
  • Patent number: 10644011
    Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 5, 2020
    Assignee: IoTMemory Technology Inc.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Yu-Ming Cheng
  • Publication number: 20180189541
    Abstract: An optical identification method for sensing a physiological feature, includes: projecting light to a physiological portion for generating reflection light from the physiological portion; receiving the reflection light, to generate an image; generating slant pattern information according to the image; transforming the slant pattern information into a pattern identification matrix; and determining the physiological feature according to the pattern identification matrix.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 5, 2018
    Inventors: Chu-Hsin Chang, Jun-Shian Hsiao, Ju-Yu Yu, Chun-Fu Lin, Yu-Ming Cheng, Hui-Min Tsai
  • Patent number: 9859291
    Abstract: A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: January 2, 2018
    Assignees: IoTMemory Technology Inc.
    Inventors: Tzung-Wen Cheng, Yu-Ming Cheng
  • Patent number: 9761596
    Abstract: A non-volatile memory having memory cells is provided. The memory cells include stack structures, floating gates, tunneling dielectric layers, erase gate dielectric layers, auxiliary gate dielectric layers, source regions, drain regions, control gates and inter-gate dielectric layers. The stacked structures include gate dielectric layers, auxiliary gates, insulating layers and erase gates. The floating gates are disposed on sidewalls on a first side of the stacked structures. The tunneling dielectric layers are disposed under the floating gates. The erase gate dielectric layers are disposed between the erase gates and floating gates. The auxiliary gate dielectric layers are disposed between the auxiliary gates and the floating gates. The source and drain regions are separately disposed on sides of the stack structures and the floating gates. The control gates are disposed on the source regions and the floating gates.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: September 12, 2017
    Assignees: IoTMemory Technology Inc.
    Inventor: Yu-Ming Cheng
  • Publication number: 20170040334
    Abstract: A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.
    Type: Application
    Filed: August 3, 2015
    Publication date: February 9, 2017
    Inventors: Tzung-Wen Cheng, Yu-Ming Cheng
  • Patent number: 9426370
    Abstract: The present invention discloses an image capturing device and an exposure time adjusting method thereof. The image capturing device comprises an image capturing module, a processing module and an image integrated module. The image capturing module is used to capture a plurality of temporary images. While the image capturing module captures the temporary images, the processing module dynamically adjusts the exposure times of the temporary images according to a predetermined file, a plurality of analysis results of the temporary images or the vibration information sensed by a vibration sensor. Next, the image integrated module controlled by a control module in the processing module integrates the temporary images to generate a stored image.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: August 23, 2016
    Assignee: Altek Corporation
    Inventors: Yun-Chin Li, Yu-Ming Cheng, Chin-Lung Yang
  • Publication number: 20160225777
    Abstract: A non-volatile memory having memory cells is provided. The memory cells include stack structures, floating gates, tunneling dielectric layers, erase gate dielectric layers, auxiliary gate dielectric layers, source regions, drain regions, control gates and inter-gate dielectric layers. The stacked structures include gate dielectric layers, auxiliary gates, insulating layers and erase gates. The floating gates are disposed on sidewalls on a first side of the stacked structures. The tunneling dielectric layers are disposed under the floating gates. The erase gate dielectric layers are disposed between the erase gates and floating gates. The auxiliary gate dielectric layers are disposed between the auxiliary gates and the floating gates. The source and drain regions are separately disposed on sides of the stack structures and the floating gates. The control gates are disposed on the source regions and the floating gates.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventor: Yu-Ming Cheng
  • Patent number: 8922678
    Abstract: The present invention discloses an electronic apparatus, an image capturing apparatus and a method thereof. The image capturing method comprises the following steps of: capturing a plurality of temporal images by an image capturing module, and setting one of the temporal images as a base image by a processing module; dividing each temporal image into a plurality of temporal image blocks, and dividing the base image into a plurality of base image blocks by the processing module; determining whether the difference between each temporal image block and the corresponding base image block is lower than a threshold value by the processing module; integrating the temporal image block and the corresponding base image block to generate a final image by the processing module when the difference between the temporal image block and the corresponding base image block is lower than the threshold value.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: December 30, 2014
    Assignee: Altek Corporation
    Inventors: Yun-Chin Li, Yu-Ming Cheng, Chin-Lung Yang