Patents by Inventor Yu-Ming Li

Yu-Ming Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11888490
    Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
  • Publication number: 20240032439
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20240030155
    Abstract: The present invention provides a wafer level chip scale package (WLCSP) unit; the WLCSP unit includes a die, a dielectric layer, and a bottom metal layer; the die has a substrate and an active surface; multiple pads are mounted on the active surface, and a soldering layer is mounted on a surface of each of the pads; the dielectric layer covers an upper part of four lateral surfaces of the die, exposing a lower part of the four lateral surfaces of the die; the bottom metal layer is mounted on a bottom surface of the substrate; the bottom metal layer protects a bottom surface of the dies, dissipates heat generated by the dies, and also protects the dies from external electromagnetic interferences (EMI).
    Type: Application
    Filed: August 10, 2022
    Publication date: January 25, 2024
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung HO, Chi-Hsueh LI, Yu-Ming HSU, Yung-Hui WANG, Chia-Wei CHEN
  • Patent number: 11855006
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20230413571
    Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Inventors: Wen-Ling LU, Yu-Chien CHIU, Chih-Yu CHANG, Hung-Wei LI, Ya-Yun CHENG, Zhiqiang WU, Yu-Ming LIN, Mauricio MANFRINI
  • Publication number: 20230410856
    Abstract: A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Inventors: Yung-Chun LI, Yu-Ming HUANG
  • Publication number: 20230386591
    Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a high-voltage (HV) driver, a global HV power switch configured to generate a HV power signal, and a HV power switch coupled between the global HV switch and the HV driver. The HV power switch is configured to, responsive to the HV power signal, output power and ground signals, each of the power signal and the ground signal having first and second voltage levels, and the HV driver is configured to output a HV activation signal to a column of the bank of NVM devices responsive to the power signal and the ground signal.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Gu-Huan LI, Chen-Ming HUNG, Yu-Der CHIH
  • Publication number: 20230387224
    Abstract: Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, and a pair of contact via structures electrically connected to the pair of active regions. The contact via structure is formed in an interlayer dielectric layer that extends over the channel layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Hung Wei LI, Mauricio MANFRINI, Sai-Hooi YEONG, Yu-Ming LIN
  • Publication number: 20230387313
    Abstract: A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Hung Wei LI, Mauricio MANFRINI, Sai-Hooi YEONG, Yu-Ming LIN
  • Publication number: 20230387024
    Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ming CHEN, Yu-Chang LIN, Chung-Ting LI, Jen-Hsiang LU, Hou-Ju LI, Chih-Pin TSAO
  • Patent number: 11817485
    Abstract: Field effect transistors and method of making. The field effect transistors include a pair of active regions in a channel layer, a channel region located between the pair of active regions and a self-aligned passivation layer located on a surface of the pair of active regions.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung Wei Li, Mauricio Manfrini, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20230359280
    Abstract: A method of customizing a hand gesture provides a touch screen, a computing unit connected with the touch screen, and a hand gesture database connected with the computing unit, and the method includes the following steps: recording a hand gesture trajectory data input of an input hand gesture on the touch screen; converting the hand gesture trajectory data input into a 2D trajectory graph of the input hand gesture; the computing unit sequentially reads a 2D hand gesture reference graph from the hand gesture database, and correspondingly generates a 2D hand gesture reference graph set for the 2D hand gesture reference graph read, and then the computing unit compares the similarity between the 2D trajectory graph of the input hand gesture and each reference graph in the 2D hand gesture reference graph set to determine whether the input hand gesture is already in the hand gesture database.
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Inventors: MIKE CHUN-HUNG WANG, GUAN-SIAN WU, CHIEH WU, YU-FENG WU, WEI-CHI LI, TSUNG-MING TAI, WEN-JYI HWANG, SIMON ANDREAS, DELLA FITRAYANI BUDIONO, FANG LI, CHING-CHIN KUO
  • Patent number: 11812669
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: November 7, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 11791006
    Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a plurality of high-voltage (HV) drivers, a global HV power switch configured to generate a HV power signal, and a plurality of HV power switches coupled to the global HV switch. A first HV power switch of the plurality of HV power switches is coupled to each HV driver of the plurality of HV drivers, the first HV power switch of the plurality of HV power switches is configured to output a power signal responsive to the HV power signal, and each HV driver of the plurality of HV drivers is configured to output a HV activation signal to a corresponding column of the bank of NVM devices responsive to the power signal.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gu-Huan Li, Chen-Ming Hung, Yu-Der Chih
  • Patent number: 11776911
    Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ming Chen, Yu-Chang Lin, Chung-Ting Li, Jen-Hsiang Lu, Hou-Ju Li, Chih-Pin Tsao
  • Publication number: 20230282482
    Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
    Type: Application
    Filed: June 4, 2022
    Publication date: September 7, 2023
    Inventors: Tsung-Han Shen, Kevin Chang, Yu-Ming Li, Chih-Hsiang Fan, Yi-Ting Wang, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Publication number: 20230238462
    Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Inventors: Hung Wei LI, Yu-Ming LIN, Mauricio MANFRINI, Kuo-Chang CHIANG, Sai-Hooi YEONG
  • Patent number: 11699655
    Abstract: A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Li, Yu-Ming Lin, Mauricio Manfrini, Sai-Hooi Yeong
  • Publication number: 20230213457
    Abstract: An automated optical double-sided inspection apparatus includes a first image-capturing portion, a second image-capturing portion, a platform, a first light-blocking portion, a second light-blocking portion, and a processing portion. The platform carries an external object. When the processing portion operates in a first capturing mode, the second light-blocking portion blocks visible light from passing therethrough, while the first light-blocking portion allows visible light to pass therethrough, so that the first image-capturing portion shoots a first side of the external object through the first light-blocking portion to obtain a first image.
    Type: Application
    Filed: December 21, 2022
    Publication date: July 6, 2023
    Inventors: Yee Siang GAN, Sze-Teng LIONG, Shih-Kai FAN, Che-Ming LI, Yu-Hsien LIN
  • Publication number: 20230198529
    Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 22, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li