Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first active region extending lengthwise along a first direction and having a first width along a second direction perpendicular to the first direction, a second active region extending lengthwise along the first direction and having a second width along the second direction, and an epitaxial feature sandwiched between the first active region and the second active region along the first direction. The first width is greater than the second width.

Abstract: A display apparatus includes a light-transmitting structural plate, some optical microscopic structures, an optical film, a base plate and some light emitting elements. The light-transmitting structural plate has a first side and a second side opposite to each other. The optical microscopic structures are regularly arrayed and formed on the first side or the second side. The optical microscopic structure has an inclined surface connecting at a connecting line and forming an angle ranging between 30 degrees and 150 degrees with a corresponding inclined surface of an adjacent one of the optical microscopic structures. The optical film is located on the first side. The base plate is separated from the second side by a space. The light emitting elements are located inside the space and disposed on the base plate. The light emitting elements respectively emit a light ray to the light-transmitting structural plate.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: An in-mold electronic (IME) device includes a curved substrate, a first conductive layer, a dielectric layer, a gap compensation layer, and a second conductive layer. The curved substrate has a first surface. The first conductive layer is disposed on the first surface. The dielectric layer is disposed on the first conductive layer and has a first thickness. The gap compensation layer is disposed on the first surface and connected to the dielectric layer. The gap compensation layer has a second thickness. The second conductive layer is disposed on the gap compensation layer and electrically connected to the gap compensation layer. A curvature radius of the curved substrate is c, a ratio of the second thickness to the first thickness is r, and c and r satisfy a relationship: r=1.5?0.02c±15%.

Abstract: A virtual metrology method using a convolutional neural network (CNN) is provided. In this method, a dynamic time warping (DTW) algorithm is used to delete unsimilar sets of process data, and adjust the sets of process data to be of the same length, thereby enabling the CNN to be used for virtual metrology. A virtual metrology model of the embodiments of the present invention includes several CNN models and a conjecture model, in which plural inputs of the CNN model are sets of time sequence data of respective parameters, and plural outputs of the CNN models are inputs to the conjecture model.

Abstract: An electronic apparatus including a compression molding board and a connection pad is provided. The compression molding board has a device bonding area and a bending area formed by compression molding. The device bonding area is different from the bending area. The connection pad is disposed on the device bonding area of the compression molding board.

Abstract: An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: A flexible hybrid electronic (FHE) system includes a carrier, a first redistribution structure on the carrier, a first device on the first redistribution structure, and an encapsulation layer encapsulating the first device. The carrier has a first Young's modulus Y1. The first redistribution structure has a second Young's modulus Y2. The first device and a portion of the encapsulation layer form a top surface of the first redistribution structure to a top surface of the first device is a first portion having a third Young's modulus Y3. The other portion of the encapsulation layer from the top surface of the first device to a top surface of the encapsulation layer is a second portion having a fourth Young's modulus Y4. A ratio of Y3/Y4 is between 1.62 and 1.98; a ratio of Y3/Y2 is between 0.18 and 0.22; and a ratio of Y3/Y1 is between 280.62 and 342.98.

Abstract: The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.

Abstract: The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.

Abstract: The present disclosure provides a semiconductor package having a size equal to or larger than standard size 0201. The semiconductor package includes a die and a packing member. The size of the die is smaller than one-half of the standard size 0201, and the packing member encapsulates the die.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second. portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.