Abstract: A two-phase immersion-type heat dissipation structure having fins for facilitating bubble generation is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the plurality of fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins and the fin surface have an included angle therebetween that is from 80 degrees to 100 degrees. A center line average roughness (Ra) of the side surface is less than 3 ?m, and a ten-point average roughness (Rz) of the side surface is not less than 12 ?m.

Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.

Abstract: Techniques are disclosed for acquiring a captured target image of a target region. When it is determined that there is at least one to-be-optimized region of a bright region and/or a dark region in the target image, calculating, for each to-be-optimized region, a pixel average of the to-be-optimized region in the target image, and determining a to-be-optimized region received dose corresponding to the pixel average of the to-be-optimized region; adjusting an X-ray emission dose of an X-ray source according to a principle of making the to-be-optimized region received dose reach an X-ray reference received dose, and acquiring optimized images of the target region captured based on the X-ray emission dose adjusted to meet a requirement; and adding and synthesizing the optimized images, or adding and synthesizing the optimized images and the target image, to obtain an X-ray image of the target region.

Abstract: The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A method for manufacturing nitride catalyst is provided, which includes putting a Ru target and an M target into a nitrogen-containing atmosphere, in which M is Ni, Co, Fe, Mn, Cr, V, Ti, Cu, or Zn. The method also includes providing powers to the Ru target and the M target, respectively. The method also includes providing ions to bombard the Ru target and the M target for depositing MxRuyN2 on a substrate by sputtering, wherein 0<x<1.3, 0.7<y<2, and x+y=2, wherein MxRuyZ2 is cubic crystal system or amorphous.

Abstract: A two-phase immersion-cooling heat-dissipation structure having skived fins with high surface roughness includes an immersion-cooling substrate and a plurality of skived fins. The immersion-cooling substrate has a top surface and a bottom surface that are opposite to each other, the bottom surface is used for contacting a heat source immersed in a two-phase coolant, the top surface is connected with the plurality of skived fins, a center line average roughness Ra of a surface of the plurality of skived fins is greater than 10 ?m, and a ten point average roughness Rz of the surface of the plurality of skived fins is greater than 20 ?m, such that a ratio between a surface area of the plurality of skived fins in contact with the two-phase coolant and a volume of the plurality of skived fins is greater than 400.

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

Abstract: A two-phase immersion-cooling heat-dissipation structure having shortened evacuation route for vapor bubbles includes an immersion-cooling substrate having a first surface and a second surface that are opposite to each other and immersion-cooling fins. The second surface contacts a heat source immersed in a two-phase coolant, and the first surface connects to the immersion-cooling fins. The immersion-cooling fins include at least one skived fin integrally formed on the first surface of the immersion-cooling substrate by skiving, and further include at least one functional fin. The functional fin is a single continuous fin extends lengthwise in a vapor bubbles evacuation direction, has a central portion corresponding in position to the heat source and upper and lower end portions located away from the heat source, and a height of the central portion is greater than at least one of a height of the upper and lower end portions.

Abstract: A two-phase immersion-cooling heat-dissipation structure having skived fins includes an immersion-cooling substrate and a plurality of immersion-cooling fins. The immersion-cooling substrate has a top surface and a bottom surface that are opposite to each other, the bottom surface is used for contacting a heat-generating component immersed in a two-phase coolant, the top surface is connected with the plurality of immersion-cooling fins, the plurality of immersion-cooling fins include at least one skived fin integrally formed on the top surface of the immersion-cooling substrate, and the plurality of immersion-cooling fins are non-linearly arranged. A thickness of any one of the plurality of immersion-cooling fins ranges from 0.1 mm to 0.35 mm, a height of any one of the plurality of immersion-cooling fins ranges from 5 mm to 10 mm, and a gap between any two of the plurality of immersion-cooling fins ranges from 0.1 mm to 0.35 mm.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A two-phase immersion-type heat dissipation device is provided. The two-phase immersion-type heat dissipation device includes a heat dissipation substrate and a plurality of reinforced fins. The heat dissipation substrate has a first surface and a second surface configured to be in contact with a heating element. The first surface is opposite to the second surface and is arranged away from the heating element. The plurality of reinforced fins are integrally formed on the first surface of the heat dissipation substrate, and a thickness of each of the plurality of reinforced fins is less than 1 mm. According to a scanning electron microscopy image of electron backscattered diffraction, a median of local misorientation distribution of the plurality of reinforced fins is greater than 1.6 times a median of local misorientation distribution of the heat dissipation substrate.

Abstract: A two-phase immersion-type composite heat dissipation device is provided, which includes a heat dissipation substrate, a plurality of fins, and a surface porous layer. The heat dissipation substrate has a first surface and a second surface. The first surface is configured to be in contact with a heat source, and the second surface is opposite to the first surface and is distant from the heat source. A projection region of the heat dissipation substrate that corresponds to the heat source is defined as a high-temperature region, and a low-temperature region is defined at an outer periphery of the high-temperature region. The fins are opposite to the heat source, and are disposed within the high-temperature region of the second surface of the heat dissipation substrate. The surface porous layer is disposed within a range of the low-temperature region of the heat dissipation substrate.

Abstract: A device includes a container for accommodating a medicament, a pressure route and a valve. The pressure route, disposed in the container, includes an extending pathway, a pressure-route inlet connected with a connecting port, and a pressure-route outlet extending toward a container bottom. The valve includes a first through hole connecting spatially the pressure-route inlet and outlet, and a valve body dividing the extending pathway into a pressure-in pathway and a pressure-out pathway. The device can convey the medicament such as a hemostatic agent more stably and smoothly to effectively avoid blocking upon a field of vision of an endoscope by the disturbed medicament while hitting a target tissue. Thereupon, the medicament can be provided more precisely, continuity of an endoscopic surgery can be improved, efficiency of hemostasis can be enhanced, and also surgery time can be substantially shortened.

Abstract: A device includes a container for accommodating a medicament, a pressure route and a valve. The pressure route, disposed in the container, includes an extending pathway, a pressure-route inlet connected with a connecting port, and a pressure-route outlet extending toward a container bottom. The valve includes a first through hole connecting spatially the pressure-route inlet and outlet, and a valve body dividing the extending pathway into a pressure-in pathway and a pressure-out pathway. The device can convey the medicament such as a hemostatic agent more stably and smoothly to effectively avoid blocking upon a field of vision of an endoscope by the disturbed medicament while hitting a target tissue. Thereupon, the medicament can be provided more precisely, continuity of an endoscopic surgery can be improved, efficiency of hemostasis can be enhanced, and also surgery time can be substantially shortened.

Abstract: Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.