Patents by Inventor Yu-Ming Ying

Yu-Ming Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12316336
    Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: May 27, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Yonghyun Shim, Yu-Ming Ying, Guansheng Li, Delong Cui, Jun Cao
  • Publication number: 20250141435
    Abstract: In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Delong Cui, Guansheng Li, Jun Cao, Yonghyun Shim, Yu-Ming Ying
  • Publication number: 20240413827
    Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Yonghyun Shim, YU-Ming Ying, Guansheng Li, Delong Cui, Jun Cao
  • Patent number: 10862424
    Abstract: A switching inductor device having a first port and a second port includes a first inductor and a second inductor with a switch circuit. The first inductor is coupled between the first port and the second port. The second inductor and the switch circuit are connected in series, and are coupled between the first port and the second port; the first inductor and the second inductor are connected in parallel when the switch circuit is turned on.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 8, 2020
    Assignee: MEDIATEK INC.
    Inventor: Yu-Ming Ying
  • Publication number: 20190245486
    Abstract: A switching inductor device having a first port and a second port includes a first inductor and a second inductor with a switch circuit. The first inductor is coupled between the first port and the second port. The second inductor and the switch circuit are connected in series, and are coupled between the first port and the second port; the first inductor and the second inductor are connected in parallel when the switch circuit is turned on.
    Type: Application
    Filed: October 2, 2018
    Publication date: August 8, 2019
    Inventor: Yu-Ming Ying
  • Patent number: 9692395
    Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 27, 2017
    Assignee: MEDIATEK INC.
    Inventors: Yu-Ming Ying, Shiue-Shin Liu
  • Publication number: 20160197599
    Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
    Type: Application
    Filed: March 10, 2016
    Publication date: July 7, 2016
    Inventors: Yu-Ming Ying, Shiue-Shin Liu
  • Patent number: 9344065
    Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: May 17, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yu-Ming Ying, Shiue-Shin Liu
  • Publication number: 20140111257
    Abstract: A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 24, 2014
    Applicant: MEDIATEK INC.
    Inventors: Yu-Ming Ying, Shiue-Shin Liu