Patents by Inventor Yu Nakanishi
Yu Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144348Abstract: The information processing apparatus acquires the first body color desired by a user as a body color of a vehicle ordered by the user. Furthermore, based on at least the appraised value of the vehicle having a first body color after a predetermined period has elapsed, the information processing apparatus determines whether or not to propose to the user to topcoat the vehicle having the second body color with an easily peelable paint of the first body color.Type: ApplicationFiled: October 26, 2023Publication date: May 2, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kenji YAMAGUCHI, Yohei NAKANISHI, Yu HAMADA
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Publication number: 20240135418Abstract: An information processing apparatus calculates a fee for applying a second coating film including an easily removable layer to a first vehicle having a first coating film applied thereon. The information processing apparatus disclosed herein has a controller that calculates a first fee defined as a fee for applying the second coating film to the first vehicle that is for lease lower than a second fee defined as a fee for applying the second coating film to the first vehicle that is not for lease. In other words, the controller calculates the first fee by subtracting a first subtraction value from the second fee.Type: ApplicationFiled: October 22, 2023Publication date: April 25, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kenji YAMAGUCHI, Yohei Nakanishi, Yu Hamada
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Publication number: 20240086111Abstract: The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.Type: ApplicationFiled: March 2, 2023Publication date: March 14, 2024Applicant: Kioxia CorporationInventors: Yu NAKANISHI, Kazuhiro HIWADA
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Patent number: 10650877Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.Type: GrantFiled: June 3, 2019Date of Patent: May 12, 2020Assignee: Toshiba Memory CorporationInventor: Yu Nakanishi
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Publication number: 20190287608Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventor: Yu NAKANISHI
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Patent number: 10373669Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.Type: GrantFiled: November 28, 2017Date of Patent: August 6, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yu Nakanishi
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Patent number: 10302358Abstract: A food heating device includes a conveying unit, a heating unit, and a suction unit. The conveying unit has an endless belt member which allows hot air to pass therethrough. The belt member has an outgoing side on which the food is placed, and a return side, wherein the outgoing side passes through a space between the heating unit and the suction unit, and the return side is disposed to face the outgoing side and avoid the space between the heating unit and the suction unit.Type: GrantFiled: July 8, 2015Date of Patent: May 28, 2019Assignee: NICHIREI FOODS INC.Inventors: Yoshito Fujimori, Hiroaki Murata, Kengo Uno, Jiro Kitamura, Kimihiro Mori, Yu Nakanishi
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Patent number: 10109212Abstract: According to one embodiment, an processing system comprises a memory, a receiver, and a transmitter. The memory stores first target information indicating a first target related to a first user, second target information indicating a second target related to a second user, a first rate indicating an achievement rate in a case where the first user has achieved the first target, and a second rate indicating an achievement rate in a case where the second user has achieved the second target. The receiving unit receives first situation information of the first user and second situation information of the second user. The transmitting unit transmits display information obtained by combining a first degree of achievement of the first target derived from the first situation information, a second degree of achievement of the second target derived from the second situation information, the first rate, and the second rate.Type: GrantFiled: March 11, 2016Date of Patent: October 23, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Marie Takada, Yu Nakanishi, Masanobu Shirakawa
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Publication number: 20180158508Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.Type: ApplicationFiled: November 28, 2017Publication date: June 7, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yu NAKANISHI
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Patent number: 9865323Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.Type: GrantFiled: March 17, 2017Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yu Nakanishi
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Patent number: 9761326Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.Type: GrantFiled: March 9, 2016Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yu Nakanishi, Daisuke Iwai, Kiwamu Watanabe, Kenji Funaoka, Tetsuya Sunata, Keigo Hara, Marie Takada
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Publication number: 20170176101Abstract: A food heating device includes a conveying unit, a heating unit, and a suction unit. The conveying unit has an endless belt member which allows hot air to pass therethrough. The belt member has an outgoing side on which the food is placed, and a return side, wherein the outgoing side passes through a space between the heating unit and the suction unit, and the return side is disposed to face the outgoing side and avoid the space between the heating unit and the suction unit.Type: ApplicationFiled: July 8, 2015Publication date: June 22, 2017Applicant: NICHIREI FOODS INC.Inventors: Yoshito FUJIMORI, Hiroaki MURATA, Kengo UNO, Jiro KITAMURA, Kimihiro MORI, Yu NAKANISHI
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Patent number: 9684459Abstract: According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.Type: GrantFiled: March 10, 2015Date of Patent: June 20, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhiro Kondo, Yu Nakanishi, Akihiko Fukui
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Publication number: 20170053544Abstract: According to one embodiment, an processing system comprises a memory, a receiver, and a transmitter. The memory stores first target information indicating a first target related to a first user, second target information indicating a second target related to a second user, a first rate indicating an achievement rate in a case where the first user has achieved the first target, and a second rate indicating an achievement rate in a case where the second user has achieved the second target. The receiving unit receives first situation information of the first user and second situation information of the second user. The transmitting unit transmits display information obtained by combining a first degree of achievement of the first target derived from the first situation information, a second degree of achievement of the second target derived from the second situation information, the first rate, and the second rate.Type: ApplicationFiled: March 11, 2016Publication date: February 23, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Marie TAKADA, Yu NAKANISHI, Masanobu SHIRAKAWA
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Publication number: 20170031755Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.Type: ApplicationFiled: March 9, 2016Publication date: February 2, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yu NAKANISHI, Daisuke IWAI, Kiwamu WATANABE, Kenji FUNAOKA, Tetsuya SUNATA, Keigo HARA, Marie TAKADA
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Publication number: 20160139822Abstract: According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.Type: ApplicationFiled: March 10, 2015Publication date: May 19, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Nobuhiro KONDO, Yu Nakanishi, Akihiko Fukui
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Publication number: 20160103478Abstract: According to embodiments, a second control unit creates parity from information loaded into a volatile second memory. When shifting from a normal mode to a sleep mode, the second control unit stores the created parity and the information loaded in the second memory into a buffer of a non-volatile first memory, and issues a power supply shutdown request. A power supply circuit shuts down power supply to the second memory and the second control unit in response to the issued power supply shutdown request.Type: ApplicationFiled: March 3, 2015Publication date: April 14, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yu NAKANISHI, Tetsuya Sunata, Atsushi Shiraishi, Fumio Hara, Keigo Hara, Takaya Horiki, Daisuke Iwai, Takashi Ogasawara, Yasuyuki Ueda
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Patent number: 9268685Abstract: According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.Type: GrantFiled: July 29, 2013Date of Patent: February 23, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Naomi Takeda, Hiroshi Yao, Arata Miyamoto, Yu Nakanishi, Daisuke Iwai
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Publication number: 20150212884Abstract: According to one embodiment, a storage device includes an encoder, a nonvolatile memory that stores user data and a parity, a magnetic disk, and a management unit that holds correspondence between a logical address and a first physical address as first conversion information, and holds correspondence between the first physical address and a second physical address as second conversion information, with the second physical address including media information indicating a medium of a storage destination and information indicating a storage position. When the user data stored in the nonvolatile memory is to be moved to the magnetic disk, the management unit updates the second physical address of the user date in the second conversion information, to a value indicating a storage destination after the movement.Type: ApplicationFiled: September 2, 2014Publication date: July 30, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yu NAKANISHI, Daisuke IWAI, Hiroshi YAO, Naomi TAKEDA, Arata MIYAMOTO, Daiki WATANABE
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Patent number: 8879349Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.Type: GrantFiled: August 6, 2013Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenichiro Yoshii, Ikuo Magaki, Naoto Oshiyama, Tokumasa Hara, Akira Yamaga, Ryo Yamaki, Kenta Yasufuku, Naomi Takeda, Yu Nakanishi, Arata Miyamoto, Naoaki Kokubun, Daisuke Iwai