Patents by Inventor Yu Nakanishi

Yu Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250054017
    Abstract: An information processing device includes a control unit. The control unit of the information processing device acquires the number of times of maintenance performed at a predetermined station during a predetermined period of time for the leased vehicle including the maintenance. The control unit of the information processing device determines a larger amount of reward to be provided to the user of the leased vehicle as the number of times of maintenance performed at a predetermined station during a predetermined period of time is smaller. The control unit of the information processing device outputs information of the determined reward.
    Type: Application
    Filed: July 15, 2024
    Publication date: February 13, 2025
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yohei NAKANISHI, Yu Hamada, Kenta Kawashima, Yuichi Mukasa, Keisuke kondo
  • Patent number: 12147710
    Abstract: The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: November 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Yu Nakanishi, Kazuhiro Hiwada
  • Publication number: 20240281370
    Abstract: According to one embodiment, a memory system includes: a nonvolatile memory including blocks each of which includes physical memory areas; and a memory controller dividing a logical address space into a plurality of banks and associating a block with each of the plurality of banks. The memory controller is configured to: selectively scan a portion related to a first bank among the plurality of banks in a table in which a physical address corresponding to a physical memory area in which valid data is stored is mapped on the logical address space; detect a first physical address corresponding to a first physical memory area in a first block associated with the first bank as a result of the scan; read first valid data stored in the first block based on the first physical address; and write the first valid data in a second block associated with the first bank.
    Type: Application
    Filed: February 20, 2024
    Publication date: August 22, 2024
    Applicant: Kioxia Corporation
    Inventors: Hirotsugu KAJIHARA, Yu NAKANISHI, Kohei OIKAWA, Kazuhiro HIWADA
  • Publication number: 20240086111
    Abstract: The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.
    Type: Application
    Filed: March 2, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Yu NAKANISHI, Kazuhiro HIWADA
  • Patent number: 10650877
    Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yu Nakanishi
  • Publication number: 20190287608
    Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Yu NAKANISHI
  • Patent number: 10373669
    Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yu Nakanishi
  • Patent number: 10302358
    Abstract: A food heating device includes a conveying unit, a heating unit, and a suction unit. The conveying unit has an endless belt member which allows hot air to pass therethrough. The belt member has an outgoing side on which the food is placed, and a return side, wherein the outgoing side passes through a space between the heating unit and the suction unit, and the return side is disposed to face the outgoing side and avoid the space between the heating unit and the suction unit.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 28, 2019
    Assignee: NICHIREI FOODS INC.
    Inventors: Yoshito Fujimori, Hiroaki Murata, Kengo Uno, Jiro Kitamura, Kimihiro Mori, Yu Nakanishi
  • Patent number: 10109212
    Abstract: According to one embodiment, an processing system comprises a memory, a receiver, and a transmitter. The memory stores first target information indicating a first target related to a first user, second target information indicating a second target related to a second user, a first rate indicating an achievement rate in a case where the first user has achieved the first target, and a second rate indicating an achievement rate in a case where the second user has achieved the second target. The receiving unit receives first situation information of the first user and second situation information of the second user. The transmitting unit transmits display information obtained by combining a first degree of achievement of the first target derived from the first situation information, a second degree of achievement of the second target derived from the second situation information, the first rate, and the second rate.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marie Takada, Yu Nakanishi, Masanobu Shirakawa
  • Publication number: 20180158508
    Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.
    Type: Application
    Filed: November 28, 2017
    Publication date: June 7, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yu NAKANISHI
  • Patent number: 9865323
    Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yu Nakanishi
  • Patent number: 9761326
    Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yu Nakanishi, Daisuke Iwai, Kiwamu Watanabe, Kenji Funaoka, Tetsuya Sunata, Keigo Hara, Marie Takada
  • Publication number: 20170176101
    Abstract: A food heating device includes a conveying unit, a heating unit, and a suction unit. The conveying unit has an endless belt member which allows hot air to pass therethrough. The belt member has an outgoing side on which the food is placed, and a return side, wherein the outgoing side passes through a space between the heating unit and the suction unit, and the return side is disposed to face the outgoing side and avoid the space between the heating unit and the suction unit.
    Type: Application
    Filed: July 8, 2015
    Publication date: June 22, 2017
    Applicant: NICHIREI FOODS INC.
    Inventors: Yoshito FUJIMORI, Hiroaki MURATA, Kengo UNO, Jiro KITAMURA, Kimihiro MORI, Yu NAKANISHI
  • Patent number: 9684459
    Abstract: According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Kondo, Yu Nakanishi, Akihiko Fukui
  • Publication number: 20170053544
    Abstract: According to one embodiment, an processing system comprises a memory, a receiver, and a transmitter. The memory stores first target information indicating a first target related to a first user, second target information indicating a second target related to a second user, a first rate indicating an achievement rate in a case where the first user has achieved the first target, and a second rate indicating an achievement rate in a case where the second user has achieved the second target. The receiving unit receives first situation information of the first user and second situation information of the second user. The transmitting unit transmits display information obtained by combining a first degree of achievement of the first target derived from the first situation information, a second degree of achievement of the second target derived from the second situation information, the first rate, and the second rate.
    Type: Application
    Filed: March 11, 2016
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Marie TAKADA, Yu NAKANISHI, Masanobu SHIRAKAWA
  • Publication number: 20170031755
    Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.
    Type: Application
    Filed: March 9, 2016
    Publication date: February 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yu NAKANISHI, Daisuke IWAI, Kiwamu WATANABE, Kenji FUNAOKA, Tetsuya SUNATA, Keigo HARA, Marie TAKADA
  • Publication number: 20160139822
    Abstract: According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command.
    Type: Application
    Filed: March 10, 2015
    Publication date: May 19, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro KONDO, Yu Nakanishi, Akihiko Fukui
  • Publication number: 20160103478
    Abstract: According to embodiments, a second control unit creates parity from information loaded into a volatile second memory. When shifting from a normal mode to a sleep mode, the second control unit stores the created parity and the information loaded in the second memory into a buffer of a non-volatile first memory, and issues a power supply shutdown request. A power supply circuit shuts down power supply to the second memory and the second control unit in response to the issued power supply shutdown request.
    Type: Application
    Filed: March 3, 2015
    Publication date: April 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yu NAKANISHI, Tetsuya Sunata, Atsushi Shiraishi, Fumio Hara, Keigo Hara, Takaya Horiki, Daisuke Iwai, Takashi Ogasawara, Yasuyuki Ueda
  • Patent number: 9268685
    Abstract: According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naomi Takeda, Hiroshi Yao, Arata Miyamoto, Yu Nakanishi, Daisuke Iwai
  • Publication number: 20150212884
    Abstract: According to one embodiment, a storage device includes an encoder, a nonvolatile memory that stores user data and a parity, a magnetic disk, and a management unit that holds correspondence between a logical address and a first physical address as first conversion information, and holds correspondence between the first physical address and a second physical address as second conversion information, with the second physical address including media information indicating a medium of a storage destination and information indicating a storage position. When the user data stored in the nonvolatile memory is to be moved to the magnetic disk, the management unit updates the second physical address of the user date in the second conversion information, to a value indicating a storage destination after the movement.
    Type: Application
    Filed: September 2, 2014
    Publication date: July 30, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yu NAKANISHI, Daisuke IWAI, Hiroshi YAO, Naomi TAKEDA, Arata MIYAMOTO, Daiki WATANABE