Patents by Inventor Yu Nishimura

Yu Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11938226
    Abstract: The present invention relates generally to compositions and methods comprising abiotic, synthetic polymers with affinity and specificity to proteins. The synthetic polymers are an improvement over biological agents by providing a simpler, less expensive, and customizable platform for binding to proteins. In one embodiment, the compositions and methods relate to synthetic polymers with affinity and specificity to vascular endothelial growth factor (VEGF). In one embodiment, the compositions are useful for treating diseases and disorders related to the overexpression of VEGF. In one embodiment, the compositions are useful for treating cancer. In one embodiment, the compositions are useful for detecting VEGF levels from biological samples. In one embodiment, the compositions are useful for detecting overexpression of VEGF from biological samples. In one embodiment, the compositions are used to diagnose cancer.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: March 26, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kenneth J. Shea, Hiroyuki Koide, Yoshiko Miura, Yu Hoshino, Yuri Nishimura, Naoto Oku
  • Publication number: 20230049764
    Abstract: Provided is a method for manufacturing a liquid ejection head substrate and a method for manufacturing a liquid ejection head capable of reducing degradation of the quality of a printed image. To this end, in formation of a liquid ejection head substrate, a part required to have more precise relative positional relation or not required to have high fabrication precision is set as a first part, and for the first part, a single-shot exposure method is employed. Also, a part required to have higher fabrication precision is set as a second part, and for the second part, a split exposure method is employed.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 16, 2023
    Inventors: Seiko Minami, Hidenori Yamato, Takaaki Yamaguchi, Nobuyuki Hirayama, Kyohei Kubota, Yu Nishimura
  • Patent number: 11177314
    Abstract: A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 16, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yu Nishimura, Sho Suzuki, Yasushi Matsuno, Yusuke Onuki, Masahiro Kobayashi, Takashi Okagawa, Yoshiyuki Nakagawa
  • Publication number: 20200335547
    Abstract: A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Yu Nishimura, Sho Suzuki, Yasushi Matsuno, Yusuke Onuki, Masahiro Kobayashi, Takashi Okagawa, Yoshiyuki Nakagawa
  • Patent number: 10763298
    Abstract: A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: September 1, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yu Nishimura, Sho Suzuki, Yasushi Matsuno, Yusuke Onuki, Masahiro Kobayashi, Takashi Okagawa, Yoshiyuki Nakagawa
  • Publication number: 20180122852
    Abstract: A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.
    Type: Application
    Filed: October 24, 2017
    Publication date: May 3, 2018
    Inventors: Yu Nishimura, Sho Suzuki, Yasushi Matsuno, Yusuke Onuki, Masahiro Kobayashi, Takashi Okagawa, Yoshiyuki Nakagawa
  • Publication number: 20180006584
    Abstract: There is provided a piezoelectric actuator apparatus capable of moving an object to be driven at high velocity by using a piezoelectric element to apply a force to a driving member coupled to the object to be driven by a predetermined frictional force. A piezoelectric actuator apparatus 100 is controlled and driven by inputting a driving voltage having a PWM waveform to a piezoelectric element 101 to which an inductor 27 and a resistor 28 are connected in series. The piezoelectric actuator apparatus 100 increases the velocity of the object to be driven 106 by adjusting respective values of the inductance L0 and the resistance R0 to control damping ratios, amplitudes, and resonance frequencies of the respective vibrations of the piezoelectric mechanical resonance and the piezoelectric electrical resonance, and inducing a response of the driving member 102 closer to sawtooth waves.
    Type: Application
    Filed: November 30, 2015
    Publication date: January 4, 2018
    Inventors: Yu Nishimura, Toshiaki Edamitsu, Hitoshi Yamagata
  • Patent number: 9559136
    Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 31, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aiko Kato, Yu Nishimura, Hiroaki Naruse, Keita Torii
  • Publication number: 20150228683
    Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.
    Type: Application
    Filed: February 10, 2015
    Publication date: August 13, 2015
    Inventors: Aiko Kato, Yu Nishimura, Hiroaki Naruse, Keita Torii