Patents by Inventor Yu-Nu Hsu

Yu-Nu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527504
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20220367398
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Publication number: 20220367396
    Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
  • Patent number: 11469198
    Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
  • Patent number: 11469203
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Publication number: 20210035937
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 10741513
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20200020655
    Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.
    Type: Application
    Filed: March 14, 2019
    Publication date: January 16, 2020
    Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
  • Publication number: 20190189577
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: June 20, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Publication number: 20190131263
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 2, 2019
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10163836
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20180166409
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: January 22, 2018
    Publication date: June 14, 2018
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 9875979
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20170141059
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 8722537
    Abstract: MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Te Huang, Chia-Hua Chu, Yu-Nu Hsu, Chun-Wen Cheng, Li-Chung Peng
  • Publication number: 20100240215
    Abstract: MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode.
    Type: Application
    Filed: January 13, 2010
    Publication date: September 23, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Te Huang, Chia-Hua Chu, Yu-Nu Hsu, Chun-Wen Cheng, Li-Chung Peng
  • Patent number: 6596417
    Abstract: The present invention provides a longitudinal magnetic recording media having a substrate, a Co or Co alloy based magnetic layer arid an underlayer disposed between the substrate and the magnetic layer. The underlayer is made of a material having a Ga3Pt5 crystalline structure, most preferably Ni5Al3. Several intermediate layers, disposed between the underlayer and the magnetic layer may also be included.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: July 22, 2003
    Assignee: Carnegie Mellon University
    Inventors: Yu-Nu Hsu, David E. Laughlin, David N. Lambeth