Patents by Inventor Yu-Pin Chang

Yu-Pin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134107
    Abstract: A light source device includes a light guide plate, an optical adhesive, and a light source element. The light guide plate includes a light guide substrate and an enhancement layer. The light guide substrate has a light incident surface, a first surface, and a second surface. The first surface is opposite to the second surface, and the light incident surface extends between the first surface and the second surface. The enhancement layer is disposed on the light guide substrate. A thickness of the enhancement layer is from 1 micrometer to 25 micrometers and a first refractive index of the light guide substrate is greater than a second refractive index of the enhancement layer. The optical adhesive is interposed between the first surface of the light guide substrate and the optical adhesive. The light source element is disposed beside the light incident surface to emit light toward the light incident surface.
    Type: Application
    Filed: June 26, 2023
    Publication date: April 25, 2024
    Applicant: E Ink Holdings Inc.
    Inventors: Hsin-Tao Huang, Yu-Chuan Wen, Jen-Pin Yu, Ching-Huan Liao, Ya-Chin Chang
  • Publication number: 20240128868
    Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Jung Chang, Shao-Ming Chang, Tsan-He Wang, Jiing-Horng Wang, Yu-Pin Tseng
  • Publication number: 20240130257
    Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.
    Type: Application
    Filed: April 21, 2023
    Publication date: April 18, 2024
    Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
  • Publication number: 20240095168
    Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen
  • Publication number: 20240095177
    Abstract: A computing system performs partial cache deactivation. The computing system estimates the leakage power of a cache based on operating conditions of the cache including voltage and temperature. The computing system further identifies a region of the cache as a candidate for deactivation based on cache hit counts. The computing system then adjusts the size of the region for the deactivation based on the leakage power and a bandwidth of a memory hierarchy device. The memory hierarchy device is at the next level to the cache in a memory hierarchy of the computing system.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen
  • Publication number: 20240087057
    Abstract: A power consumption monitoring device includes a sensor, a storage, and a processor. The sensor is configured to detect a power-consuming device quantity and a power consumption amount. The storage is configured to store the power-consuming device quantity and the power consumption amount. The processor is communicatively connected to the sensor and the storage. The processor is configured to calculate a power-consuming device idling indicator based on the power-consuming device quantity and the power consumption amount in a monitoring time interval, wherein the power-consuming device idling indicator is used for indicating a deviation status of the power-consuming device quantity and the power consumption amount. The processor is further configured to determine whether the power-consuming device idling indicator exceeds a warning threshold. In response to the power-consuming device idling indicator exceeding the warning threshold, the processor is further configured to generate a warning message.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 14, 2024
    Inventors: Wei-Chao CHEN, Ming-Chi CHANG, Chih-Pin WEI, Ke-Li WU, Hua-Hsiu CHIANG, Yu-Lun CHANG
  • Patent number: 11921101
    Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei Chang, Chiung-Han Wang
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Publication number: 20200020094
    Abstract: An artificial intelligence-based leather inspection method and leather product production method includes the step of using sensor means to obtain a leather data of a leather raw material, then the step of inputting the leather data to an artificial intelligence module to determine a defective area and a non-defective area of the leather raw material, the step of establishing an area data after judgment of the defective area and the non-defective area and then using the area data to define the non-defective area into one or multiple reserved areas so that the leather raw material can be cut into leather components corresponding to the respective reserved areas.
    Type: Application
    Filed: October 10, 2018
    Publication date: January 16, 2020
    Inventor: Yu-Pin CHANG
  • Patent number: 9697780
    Abstract: A liquid crystal display (LCD) device includes: a data source, for generating a N-bit pixel data, N being a positive integer; a digital gamma correction unit, coupled to the data source, for performing digital gamma correction on the pixel data to generate a (N+M)-bit digital gamma correction pixel data, M being a positive integer; an image dithering unit, coupled to the digital gamma correction unit, for performing image dithering on the digital gamma correction pixel data to generate a (N+M?K)-bit dithering compensation pixel data, K being a positive integer; and a converter, coupled to the image dithering unit, for converting the dithering compensation pixel data into an output image. A bit number of the converter is lower than a bit number of the digital gamma correction unit.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: July 4, 2017
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Yu-Pin Chang, Kai-I Dai, Jie-Jung Huang
  • Patent number: 9692462
    Abstract: A transmitter includes a first pre-distortion circuit, a second pre-distortion circuit, a transmitting circuit and a pre-distortion parameters generating circuit. The first pre-distortion circuit uses a plurality of first pre-distortion parameters to perform a pre-distortion operation upon a first input signal to generate a pre-distorted first input signal. The second pre-distortion circuit uses a plurality of second pre-distortion parameters to perform a pre-distortion operation upon a second input signal to generate a pre-distorted second input signal. The transmitting circuit is arranged to process the pre-distorted first input signal and the pre-distorted second input signal to generate an output signal. The pre-distortion parameters generating circuit generates the first pre-distortion parameters and the second pre-distortion parameters according to the first input signal, the second input signal and the output signal.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 27, 2017
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Pin Chang
  • Patent number: 9627318
    Abstract: In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ling Mei Lin, Chun Li Wu, Yu-Pin Chang
  • Publication number: 20160269057
    Abstract: A transmitter includes a first pre-distortion circuit, a second pre-distortion circuit, a transmitting circuit and a pre-distortion parameters generating circuit. The first pre-distortion circuit uses a plurality of first pre-distortion parameters to perform a pre-distortion operation upon a first input signal to generate a pre-distorted first input signal. The second pre-distortion circuit uses a plurality of second pre-distortion parameters to perform a pre-distortion operation upon a second input signal to generate a pre-distorted second input signal. The transmitting circuit is arranged to process the pre-distorted first input signal and the pre-distorted second input signal to generate an output signal. The pre-distortion parameters generating circuit generates the first pre-distortion parameters and the second pre-distortion parameters according to the first input signal, the second input signal and the output signal.
    Type: Application
    Filed: December 21, 2015
    Publication date: September 15, 2016
    Inventor: Yu-Pin Chang
  • Patent number: 9373291
    Abstract: A method for mapping an input grayscale into an output luminance includes selecting a reference grayscale and a curvature according to an input grayscale; and generating an output luminance according to the reference grayscale, the curvature, and the input grayscale.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: June 21, 2016
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yu-Hsing Chuang, Chih-Yuan Yang, Yu-Pin Chang, Feng-Ting Pai
  • Patent number: 9318061
    Abstract: A method for mapping an input grayscale into an output luminance includes selecting a first reference grayscale, a first reference luminance, a second reference grayscale and a second reference luminance according to an input grayscale, generating a middle reference grayscale and a middle luminance, replacing a value of the first or second reference grayscale by a value of the middle reference grayscale, and replacing a value of the first or second reference luminance by a value of the middle luminance according to the middle reference grayscale and the input grayscale, and generating an output luminance by computing a linear transformation equation.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 19, 2016
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yu-Pin Chang, Kai-I Dai, Jie-Jung Huang, Yu-Hsing Chuang, Shih-Hung Huang
  • Publication number: 20160019850
    Abstract: A method for mapping an input grayscale into an output luminance includes selecting a reference grayscale and a curvature according to an input grayscale; and generating an output luminance according to the reference grayscale, the curvature, and the input grayscale.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 21, 2016
    Inventors: Yu-Hsing Chuang, Chih-Yuan Yang, Yu-Pin Chang, Feng-Ting Pai
  • Publication number: 20160019849
    Abstract: A method for mapping an input grayscale into an output luminance includes selecting a first reference grayscale, a first reference luminance, a second reference grayscale and a second reference luminance according to an input grayscale, generating a middle reference grayscale and a middle luminance, replacing a value of the first or second reference grayscale by a value of the middle reference grayscale, and replacing a value of the first or second reference luminance by a value of the middle luminance according to the middle reference grayscale and the input grayscale, and generating an output luminance by computing a linear transformation equation.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 21, 2016
    Inventors: Yu-Pin Chang, Kai-I Dai, Jie-Jung Huang, Yu-Hsing Chuang, Shih-Hung Huang
  • Publication number: 20150364420
    Abstract: In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Inventors: LING MEI LIN, CHUN LI WU, YU-PIN CHANG
  • Patent number: 9196210
    Abstract: The present invention discloses a driving module for a liquid crystal display device. The driving module includes a data line signal processing unit, for generating a plurality of data driving signals, a scan line signal processing unit, for generating a plurality of gate driving signals, and a control unit, for controlling the data line signal processing unit and the gate line signal processing unit, such that a plurality of sub-pixels corresponding to a data line are with different charging orders in different frames, or are charged with different charging periods in a same frame.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: November 24, 2015
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yu-Pin Chang, Chih-Peng Hsia, Tsung-Yin Yu
  • Patent number: 9098915
    Abstract: An image processing apparatus for adjusting the luminance of a target pixel of an image is provided. The target pixel includes original pixel data and corresponds to a mask value. The image processing apparatus includes a luminance detection unit, a luminance compensation unit and a mapping unit. The luminance detection unit generates an original luminance value according to the original pixel data. The luminance compensation unit adjusts the original luminance value according to a non-linear function to generate a compensated luminance value. The mapping unit generates adjusted pixel data according to the compensated luminance value. The non-linear function at least includes a first monomial function, which has a base part associated with an inverse value of the original luminance value and an exponent part associated with the mask value.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: August 4, 2015
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Yu-Hsing Chuang, Yu-Pin Chang, Chih-Yuan Yang, Feng-Ting Pai