Patents by Inventor Yu-Pin Tsai
Yu-Pin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230228920Abstract: A composite optical film comprises a first optical film and a second optical film disposed on the first optical film, wherein the first optical film comprises a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate; and the second optical film comprises a first PET film thereon having a first set of prisms and a second PET film having a second set of prisms thereon, wherein the first PET film and the second PET film are laminated together.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Inventors: Yi-Long Tyan, Ching-An Yang, Yu-Mei Juan, Hsin-Yi Tsai, Yu-Cheng Hsiao, Lung-Pin Hsin, Hui-Yong Chen
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Publication number: 20230078564Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: ApplicationFiled: November 18, 2022Publication date: March 16, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Meng-Wei HSIEH, Yu-Pin TSAI
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Patent number: 11508668Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: GrantFiled: December 3, 2020Date of Patent: November 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
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Publication number: 20220181268Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Meng-Wei HSIEH, Yu-Pin TSAI
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Publication number: 20220020885Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.Type: ApplicationFiled: September 28, 2021Publication date: January 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Pin TSAI, Tsung-Yueh TSAI, Teck-Chong LEE
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Patent number: 11133423Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.Type: GrantFiled: July 3, 2019Date of Patent: September 28, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee
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Patent number: 11121111Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.Type: GrantFiled: September 9, 2019Date of Patent: September 14, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Pin Tsai, Ming-Chi Liu, Yu-Ting Lu, Kai-Chiang Hsu, Che-Ting Liu
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Patent number: 11088057Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.Type: GrantFiled: May 10, 2019Date of Patent: August 10, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Publication number: 20210074664Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.Type: ApplicationFiled: September 9, 2019Publication date: March 11, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
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Publication number: 20210005761Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Pin TSAI, Tsung-Yueh TSAI, Teck-Chong LEE
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Patent number: 10879215Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.Type: GrantFiled: March 8, 2019Date of Patent: December 29, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Publication number: 20200357730Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
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Patent number: 10395997Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.Type: GrantFiled: January 18, 2017Date of Patent: August 27, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Cheng Tsao, Cheng-Hung Wang, Chun-Chieh Lin, Hsiu-Hsiung Yang, Yu-Pin Tsai
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Publication number: 20190206843Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
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Patent number: 10269771Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.Type: GrantFiled: August 11, 2017Date of Patent: April 23, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
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Patent number: 10037975Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.Type: GrantFiled: August 11, 2017Date of Patent: July 31, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng
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Publication number: 20180061727Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.Type: ApplicationFiled: August 11, 2017Publication date: March 1, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
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Publication number: 20180061813Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.Type: ApplicationFiled: August 11, 2017Publication date: March 1, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Li-Hao LYU
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Publication number: 20170125310Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Cheng TSAO, Cheng-Hung WANG, Chun-Chieh LIN, Hsiu-Hsiung YANG, Yu-Pin TSAI
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Patent number: 9564376Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.Type: GrantFiled: September 23, 2014Date of Patent: February 7, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Cheng Tsao, Cheng-Hung Wang, Chun-Chieh Lin, Hsiu-Hsiung Yang, Yu-Pin Tsai