Abstract: A switching regulator includes: a power stage circuit configured to operably control a power switch therein according to a pulse width modulation signal to switch an inductor coupled to a phase node, so as to convert an input voltage to an output voltage; and a control circuit configured to operably determine an equivalent capacitance adjustment procedure to enter or sustain an enabled state according to a phase node voltage at the phase node at an inductor magnetization start time point in a discontinuous conduction mode (DCM) to adjust an equivalent capacitance at the phase node, so as to reduce a voltage across the power switch at another inductor magnetization start time point after the equivalent capacitance adjustment procedure.

Abstract: A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.

Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.

Abstract: A light emitting diode (LED) driver circuit is configured to drive plural LEDs which are respectively coupled to m scan-lines and n data-lines, wherein m and n are both integers greater than or equal to one. During a driving stage, each of the LEDs is controlled to emit light according to the electrical characteristics on the corresponding scan-line and on the corresponding data-line where the LED is coupled to. The LED driver circuit includes: a power saving control circuit which includes a storage capacitor; a pre-discharging circuit configured to pre-discharge the charges on the m scan-lines to the storage capacitor during a pre-discharging stage; and a pre-charging circuit configured to pre-charge the n data-lines by the charges stored in the storage capacitor during a pre-charging stage.