Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: The present application provides a method for manufacturing a memory device having a word line (WL) with dual conductive materials. The method includes steps of providing a semiconductor substrate with an active area defined adjacent to a surface of the semiconductor substrate; forming a recess extending from the surface into the semiconductor substrate; disposing a first insulating layer conformal to the recess; disposing a first conductive material within the recess and surrounded by the first insulating layer; removing a portion of the first conductive material to form a first conductive member; disposing a second insulating layer within the recess and conformal to the first insulating layer and the first conductive member; and disposing a second conductive material within the recess and surrounded by the second insulating layer to form a second conductive member adjacent to the first conductive member.

Abstract: The present application provides a memory device having a word line (WL) with dual conductive materials. The memory device includes a semiconductor substrate with an active area defined adjacent to a surface of the semiconductor substrate, wherein the semiconductor substrate includes a recess extending from the surface into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes a first insulating layer disposed within and conformal to the recess, a first conductive member surrounded by the first insulating layer and disposed within the recess, a second insulating layer disposed conformal to the first insulating layer and the first conductive member, and a second conductive member disposed adjacent to the first conductive member and surrounded by the second insulating layer.

Abstract: A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.

Abstract: A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.

Abstract: A semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a first well region, and a first structure. The substrate has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is in the substrate and between the first gate structure and the second gate structure. The first structure is disposed in the first well region. A shape of the first structure has an acute angle.

Abstract: The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.

Abstract: A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.

Abstract: This document describes radar tracking with model estimates augmented by radar detections. An example tracker analyzes information derived using radar detections to enhance radar tracks having object measurements estimated from directly analyzing data cubes with a model (e.g., a machine-learning model). High-quality tracks with measurements to objects of importance can be quickly produced with the model. However, the model only estimates measurements for classes of objects its training or programming can recognize. To improve estimated measurements from the model, or even in some cases, to convey additional classes of objects, the tracker separately analyzes detections. Detections that consistently align to objects recognized by the model can update model-derived measurements conveyed initially in the tracks. Consistently observed detections that do not align to existing tracks may be used to establish new tracks for conveying more classes of objects than the model can recognize.

Abstract: This document describes techniques and systems related to tracking different sections of articulated vehicles. A vehicle uses a radar system that can discern between unarticulated vehicles and articulated vehicles, which by definition have multiple sections that can pivot in different directions for turning or closely following a curve. The radar system obtains detections indicative of another vehicle traveling nearby. When the detections indicate the other vehicle is articulated, the radar system tracks each identifiable section, rather than tracking all the sections together. A bounding box is generated for each identifiable section; the radar system separately and concurrently monitors a velocity of each bounding box. The multiple bounding boxes that are drawn enable the radar system to accurately track each connected section of the articulated vehicle, including to detect whether any movement occurs between two connected sections, for accurately localizing the vehicle when driving.

Abstract: A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.

Abstract: A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.

Abstract: A filter material and a manufacturing method thereof are provided. The manufacturing method includes hydrophilizing the filter material by supercritical fluid processing technology, so as to filter out white blood cells in the blood.

Abstract: Systems and methods for detecting a motor developmental delay and/or neurodevelopmental disorder of an infant are described herein. An example method can include receiving motion data associated with the infant's gross motor activity; analyzing, using a machine learning algorithm, the motion data to detect a kinematic feature; comparing the kinematic feature to an expected relationship between the kinematic feature and infant age; and detecting the neurodevelopmental disorder based on the comparison. An infant sensor suit is also described herein. An example infant sensor suit can include an article of clothing; a plurality of sensors; a power source operably coupled to the sensors; and a wireless transmitter operably coupled to the sensors. The sensors, power source, and wireless transmitter can be incorporated into the article of clothing.