Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A fixed-on-time controller utilizing an adaptive saw signal for discontinuous mode PFC power conversion, the fixed-on-time controller comprising: an error amplifier, having a negative input end coupled to a feedback signal, a positive input end coupled to a reference voltage, and an output end for providing a threshold signal; an adaptive current source generator, used to generate an adaptive current source according to the threshold signal; a capacitor, charged by the adaptive current source, being used for carrying a saw signal; a switch, used to discharge the capacitor under the control of a reset signal; and a comparator, having a negative input end coupled to the threshold signal, a positive input end coupled to the saw signal, and an output end for providing a turn-off signal; and a fixed-on-time driver circuit, used to provide a driving signal and the reset signal according to the turn-off signal and a sensing signal.

Abstract: A fixed-on-time controller utilizing an adaptive saw signal for discontinuous mode PFC power conversion, the fixed-on-time controller comprising: an error amplifier, having a negative input end coupled to a feedback signal, a positive input end coupled to a reference voltage, and an output end for providing a threshold signal; an adaptive current source generator, used to generate an adaptive current source according to the threshold signal; a capacitor, charged by the adaptive current source, being used for carrying a saw signal; a switch, used to discharge the capacitor under the control of a reset signal; and a comparator, having a negative input end coupled to the threshold signal, a positive input end coupled to the saw signal, and an output end for providing a turn-off signal; and a fixed-on-time driver circuit, used to provide a driving signal and the reset signal according to the turn-off signal and a sensing signal.

Abstract: A new method of forming gate conductor lines for a DRAM in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. Active areas are defined. A gate conductor layer is deposited overlying the semiconductor substrate. The gate conductor layer is patterned to form gate conductor lines. The intersections of the gate conductor lines and the active areas form DRAM transistors. Adjacent gate conductor lines are spaced a first minimum distance in critical regions and are spaced a second minimum distance in non-critical regions. The critical regions are defined as the active areas between adjacent gate conductor lines where bit line contacts are planned. The non-critical regions are defined as areas located between the critical regions and the adjacent gate conductor lines. The second minimum distance is greater than the first minimum distance to thereby decrease the aspect ratio in the non-critical regions to less than the aspect ratio in the critical regions.

Abstract: A new method of forming gate conductor lines for a DRAM in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. Active areas are defined. A gate conductor layer is deposited overlying the semiconductor substrate. The gate conductor layer is patterned to form gate conductor lines. The intersections of the gate conductor lines and the active areas form DRAM transistors. Adjacent gate conductor lines are spaced a first minimum distance in critical regions and are spaced a second minimum distance in non-critical regions. The critical regions are defined as the active areas between adjacent gate conductor lines where bit line contacts are planned. The non-critical regions are defined as areas located between the critical regions and the adjacent gate conductor lines. The second minimum distance is greater than the first minimum distance to thereby decrease the aspect ratio in the non-critical regions to less than the aspect ratio in the critical regions.

Abstract: The method of the present invention forms a thin oxide layer on the circumferential wall of a recess in a trench and, at the same time, forms a thick oxide layer on the bottom surface of the recess. The thick oxide layer serves as the trench top oxide and the thin oxide layer serves as the gate oxide.