Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: A display device including a display area and a non-display area is provided. The display area includes a display panel, a switch unit and a first reflective film. The non-display area includes a second reflective film. The switch unit is disposed on the display panel. The first reflective film is disposed between the display panel and the switch unit. When the display device is set in a pattern mode, the display panel does not emit image light. For the pattern mode, the reflectivity in the display area is approximately equal to the reflectivity in the non-display area for ambient light.

Abstract: A display device including a display area and a non-display area is provided. The display area includes a display panel, a switch unit and a first reflective film. The non-display area includes a second reflective film. The switch unit is disposed on the display panel. The first reflective film is disposed between the display panel and the switch unit. When the display device is set in a pattern mode, the display panel does not emit image light. For the pattern mode, the reflectivity in the display area is approximately equal to the reflectivity in the non-display area for ambient light.

Abstract: A pixel array includes pixel unit sets each including a substrate having first and second pixel regions, a scan line, first and second data lines extending along a second direction, first and second active devices respectively in the first and second pixel regions, and first and second pixel electrodes respectively located in the first and second pixel regions and electrically connected to the first and second active devices, respectively. The scan line includes a main scan line and first and second branch scan lines (connected to the main scan line) extending along a first direction. The first active device is electrically connected to the first branch scan line and the first data line. The second active device is electrically connected to the second branch scan line and the second data line. At least one of the first and second data lines is overlapped with the first and second pixel electrodes.

Abstract: A pixel array includes pixel unit sets each including a substrate having first and second pixel regions, a scan line, first and second data lines extending along a second direction, first and second active devices respectively in the first and second pixel regions, and first and second pixel electrodes respectively located in the first and second pixel regions and electrically connected to the first and second active devices, respectively. The scan line includes a main scan line and first and second branch scan lines (connected to the main scan line) extending along a first direction. The first active device is electrically connected to the first branch scan line and the first data line. The second active device is electrically connected to the second branch scan line and the second data line. At least one of the first and second data lines is overlapped with the first and second pixel electrodes.

Abstract: The present disclosure discloses a display. The display includes a plurality of first pixels, a plurality of second pixels and a light-shielding unit. The second pixels are disposed around the first pixels. The light-shielding unit is disposed around the second pixels. Each of the second pixels is a white pixel, and the second pixels are sandwiched between the light-shielding unit and the first pixels.

Abstract: A pixel array includes pixel unit sets each including a substrate having first and second pixel regions, a scan line, first and second data lines extending along a second direction, first and second active devices respectively in the first and second pixel regions, and first and second pixel electrodes respectively located in the first and second pixel regions and electrically connected to the first and second active devices, respectively. The scan line includes a main scan line and first and second branch scan lines (connected to the main scan line) extending along a first direction. The first active device is electrically connected to the first branch scan line and the first data line. The second active device is electrically connected to the second branch scan line and the second data line. At least one of the first and second data lines is overlapped with the first and second pixel electrodes.

Abstract: A pixel array includes pixel unit sets each including a substrate having first and second pixel regions, a scan line, first and second data lines extending along a second direction, first and second active devices respectively in the first and second pixel regions, and first and second pixel electrodes respectively located in the first and second pixel regions and electrically connected to the first and second active devices, respectively. The scan line includes a main scan line and first and second branch scan lines (connected to the main scan line) extending along a first direction. The first active device is electrically connected to the first branch scan line and the first data line. The second active device is electrically connected to the second branch scan line and the second data line. At least one of the first and second data lines is overlapped with the first and second pixel electrodes.

Abstract: A color filter substrate is provided. The color filter substrate has a plurality of first sub-pixel areas and a plurality of second sub-pixel areas. The color filter substrate includes a first substrate, a plurality of first filters, a plurality of second filters, and a plurality of protrusions. The plurality of first filters are disposed on the first substrate and respectively located in the plurality of first sub-pixel areas. The plurality of second filters is disposed on the first substrate and respectively located in the plurality of second sub-pixel areas. The color of the first filters is different from that of the second filters. The protrusions are disposed on the first substrate and adjacent to two of the first sub-pixel areas adjacent to each other.

Abstract: A display panel includes a first substrate, a second substrate, signal lines, sub-pixels, and at least one thickness adjusting layer. The second substrate is disposed above the first substrate and has a transparent electrode layer thereon. The signal lines are disposed on the first substrate. The sub-pixels are arranged between the first and second substrates. The sub-pixels are electrically connected with the signal lines, and parts of them have at least one transparent area and at least one reflective area. The transparent area has a transparent electrode therein, and the reflective area has a reflective electrode therein, respectively. The thickness adjusting layer is disposed above the reflective electrode and located at the reflective area of the part of the sub-pixels.

Abstract: A method of manufacturing a liquid crystal display panel is provided. A photo-alignment layer and a patterned pixel electrode are formed on a first and a second substrates respectively. A liquid crystal layer is formed between the photo-alignment layer and the patterned pixel electrode. The patterned pixel electrode includes intersected electrodes having a first directional portion and a second directional portion intersected therewith, and stripe electrodes having slits therebetween connect at least one of the first directional portion and the second directional portion. When an electric field between the first and the second substrates is substantially zero, the liquid crystal molecules near the photo-alignment layer have a pre-tilt angle while those on another side are substantially perpendicular to the second substrate. As the liquid crystal layer is driven, the liquid crystal molecules of the liquid crystal layer are substantially arranged along an extending direction of the slits.

Abstract: A display panel includes a first substrate, a second substrate, signal lines, sub-pixels, and at least one thickness adjusting layer. The second substrate is disposed above the first substrate and has a transparent electrode layer thereon. The signal lines are disposed on the first substrate. The sub-pixels are arranged between the first and second substrates. The sub-pixels are electrically connected with the signal lines, and parts of them have at least one transparent area and at least one reflective area. The transparent area has a transparent electrode therein, and the reflective area has a reflective electrode therein, respectively. The thickness adjusting layer is disposed above the reflective electrode and located at the reflective area of the part of the sub-pixels.

Abstract: A method for manufacturing a liquid crystal display panel is provided. A photo-alignment layer is formed on a first substrate. Patterned pixel electrodes including intersected electrodes and stripe electrodes are formed on a second substrate. A liquid crystal layer is formed between the photo-alignment layer and the patterned pixel electrodes. Each intersected electrode has a first directional portion and a second directional portion interlacing thereto. The stripe electrodes with silts connect the first and/or the second directional portions. When an electric field between the first and the second substrates is substantially zero, liquid crystal molecules near the photo-alignment layer are arranged at a pre-tilt angle, while those disposed at another side near the second substrate are substantially perpendicular to the second substrate. As the liquid crystal layer is driven, the liquid crystal molecules of the liquid crystal layer are substantially arranged along an extending direction of the slits.

Abstract: A method for manufacturing a liquid crystal display panel is provided. A photo-alignment layer is formed on a first substrate. Patterned pixel electrodes including intersected electrodes and stripe electrodes are formed on a second substrate. A liquid crystal layer is formed between the photo-alignment layer and the patterned pixel electrodes. Each intersected electrode has a first directional portion and a second directional portion interlacing thereto. The stripe electrodes with silts connect the first and/or the second directional portions. When an electric field between the first and the second substrates is substantially zero, liquid crystal molecules near the photo-alignment layer are arranged at a pre-tilt angle, while those disposed at another side near the second substrate are substantially perpendicular to the second substrate. As the liquid crystal layer is driven, the liquid crystal molecules of the liquid crystal layer are substantially arranged along an extending direction of the slits.

Abstract: A method of manufacturing a liquid crystal display panel is provided. A photo-alignment layer and a patterned pixel electrode are formed on a first and a second substrates respectively. A liquid crystal layer is formed between the photo-alignment layer and the patterned pixel electrode. The patterned pixel electrode includes intersected electrodes having a first directional portion and a second directional portion intersected therewith, and stripe electrodes having slits therebetween connect at least one of the first directional portion and the second directional portion. When an electric field between the first and the second substrates is substantially zero, the liquid crystal molecules near the photo-alignment layer have a pre-tilt angle while those on another side are substantially perpendicular to the second substrate. As the liquid crystal layer is driven, the liquid crystal molecules of the liquid crystal layer are substantially arranged along an extending direction of the slits.