Abstract: A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing.