Patents by Inventor Yu Qing Cheng

Yu Qing Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9451043
    Abstract: The present invention includes various embodiments of a mobile app remote virtualization system and process that enables users of remote client devices to control mobile apps running in a host server environment. The resulting user experience is practically equivalent to running native mobile apps, even when such mobile apps require access to local client device resources, as well as when native versions of such mobile apps do not exist for the user's client device. The functionality afforded by the mobile app remote virtualization system and process of the present invention enables a variety of novel scenarios and “use cases” that have not previously been available to mobile device users.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 20, 2016
    Assignee: EVIE LABS, INC.
    Inventors: David Zhao, Yu Qing Cheng, Russ D'Sa, David Schwartz
  • Publication number: 20150082239
    Abstract: The present invention includes various embodiments of a mobile app remote virtualization system and process that enables users of remote client devices to control mobile apps running in a host server environment. The resulting user experience is practically equivalent to running native mobile apps, even when such mobile apps require access to local client device resources, as well as when native versions of such mobile apps do not exist for the user's client device. The functionality afforded by the mobile app remote virtualization system and process of the present invention enables a variety of novel scenarios and “use cases” that have not previously been available to mobile device users. One such use case involves encouraging users to click-thru interactive advertisements by displaying a transformed (e.g., blurred) version of the ad target in the background, and overlaying the interactive ad components that comprise the ad preroll.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 19, 2015
    Applicant: Curious Olive, Inc.
    Inventors: David Zhao, Yu Qing Cheng, Russ D'Sa, David Schwartz
  • Publication number: 20150081764
    Abstract: The present invention includes various embodiments of a mobile app remote virtualization system and process that enables users of remote client devices to control mobile apps running in a host server environment. The resulting user experience is practically equivalent to running native mobile apps, even when such mobile apps require access to local client device resources, as well as when native versions of such mobile apps do not exist for the user's client device. The functionality afforded by the mobile app remote virtualization system and process of the present invention enables a variety of novel scenarios and “use cases” that have not previously been available to mobile device users.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: Curious Olive, Inc.
    Inventors: David Zhao, Yu Qing Cheng, Russ D'Sa, David Schwartz
  • Patent number: 8941672
    Abstract: Embodiments of the present disclosure provide techniques for identifying a display when a graphics processing unit (GPU) connected to the display via a display control bus is in a low power state. By providing a separate microcontroller with a parallel connection to the display control bus, the microcontroller may detect the presence of a display device even when the GPU is in the low power state. In response to detecting the display device, the microcontroller may notify a motherboard chipset (e.g., via an interrupt) prompting the motherboard chipset to initiate a sequence to bring the GPU out of the low power state.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Rambod Jacoby, David Wyatt, Yu Qing Cheng, Ludger Mimberg
  • Patent number: 8543843
    Abstract: A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 24, 2013
    Assignees: Sun Microsystems, Inc., Sun Microsystems Technology Ltd.
    Inventors: Yu Qing Cheng, John Gregory Favor, Peter N. Glaskowsky, Carlos Puchol, Seungyoon Peter Song
  • Patent number: 8539039
    Abstract: A system in which computer content is encoded at low latency and distributed to one or more client devices and in which user gestures on the client device are translated into a digital representation of the computer's native input format, thereby allowing the client device to control the computer. A method of capturing screen data on a desktop system, packaging the captured content, streaming the content to one or more client device, decoding the content on the client-side, displaying the decoded content on the client device, accepting user input, transmitting the user input to the desktop system, translating the input into a native format, and controlling the desktop system using the translated user input.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: September 17, 2013
    Assignee: Splashtop Inc.
    Inventors: Philip Sheu, Yu Qing Cheng, Ching-Hsu Hsiao, Kay Chen, Mark Lee, Robert Ha, Thomas Deng
  • Patent number: 8373707
    Abstract: One embodiment of the present invention sets forth a technique for selecting a boot VGA adapter in a multiple VGA adapter system by controlling the system boot process using the VBIOS display detection service and boot flags that are stored in non-volatile platform memory. The SBIOS initiates a first boot that selects the motherboard integrated graphics processing unit (MGPU) as the boot VGA adapter. During this first boot, if the SBIOS determines that there are display devices attached to the MGPU, then the first boot completes normally. Otherwise, the SBIOS aborts the first boot and initiates a second boot that selects a secondary, discrete graphics processing unit GPU (DGPU) as the boot VGA adapter. During this second boot, if the SBIOS determines that there are display devices attached to the DGPU, then the second boot completes normally.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: February 12, 2013
    Assignee: NVIDIA Corporation
    Inventors: David Wyatt, Hon Fei Chong, Yu Qing Cheng
  • Publication number: 20120265803
    Abstract: A platform and service are provided that allow a user to have and use a personal, e.g. virtual, private cloud to which the user grants access to a defined group of users across multiple, different types of devices.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 18, 2012
    Inventors: Robert HA, Jian-Jung Shiu, Mark Lee, Philip Sheu, Yu Qing Cheng
  • Publication number: 20120266079
    Abstract: Mechanisms are provided that improve the usability of remote access between different devices or with different platforms by predicting user intent and, based in part on the prediction, offering the user appropriate interface tools or modifying the present interface accordingly. Mechanisms for creating and using gesture maps that improve usability between cross-device user interfaces are also provided.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 18, 2012
    Inventors: Mark Lee, Kay Chen, Yu Qing Cheng
  • Patent number: 8281308
    Abstract: A virtual core management system including a first physical core and a second physical core, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a first temperature sensor configured to sense a temperature of the first physical core and a second temperature sensor configured to sense a temperature of the second physical core, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the temperature of the first physical core and the temperature of the second physical core.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 2, 2012
    Assignee: Oracle America, Inc.
    Inventors: Yu Qing Cheng, John Gregory Favor, Peter N. Glaskowsky, Carlos Puchol, Seungyoon Peter Song
  • Patent number: 8225315
    Abstract: A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 17, 2012
    Assignees: Oracle America, Inc., Sun Microsystems Technology Ltd.
    Inventors: Yu Qing Cheng, John Gregory Favor, Peter N. Glaskowsky, Laurent R. Moll, Carlos Puchol, Joseph Rowlands, Seungyoon Peter Song
  • Patent number: 8219788
    Abstract: A virtual core management system including a first physical core having a first utilization constraint, a second physical core having a second utilization constraint, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a utilization indicator configured to measure a utilization of the first physical core with respect to the first utilization constraint and measure a utilization of the second physical core with respect to the second utilization constraint, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the utilization of the first physical core and the utilization of the second physical core.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 10, 2012
    Assignee: Oracle America, Inc.
    Inventors: Yu Qing Cheng, Peter N. Glaskowsky, Carlos Puchol, Seungyoon Peter Song
  • Publication number: 20110314093
    Abstract: A system in which computer content is encoded at low latency and distributed to one or more client devices and in which user gestures on the client device are translated into a digital representation of the computer's native input format, thereby allowing the client device to control the computer. A method of capturing screen data on a desktop system, packaging the captured content, streaming the content to one or more client device, decoding the content on the client-side, displaying the decoded content on the client device, accepting user input, transmitting the user input to the desktop system, translating the input into a native format, and controlling the desktop system using the translated user input.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 22, 2011
    Inventors: Philip Sheu, Yu Qing Cheng, Ching-Hsu Hsiao, Kay Chen, Mark Lee, Robert Ha, Thomas Deng
  • Patent number: 7958312
    Abstract: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: June 7, 2011
    Assignee: Oracle America, Inc.
    Inventors: Laurent R. Moll, Yu Qing Cheng, Peter N. Glaskowsky, Seungyoon Peter Song
  • Patent number: 7904659
    Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 8, 2011
    Assignee: Oracle America, Inc.
    Inventors: Laurent R. Moll, Yu Qing Cheng, Peter N. Glaskowsky, Seungyoon Peter Song
  • Patent number: 7899990
    Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 1, 2011
    Assignee: Oracle America, Inc.
    Inventors: Laurent R. Moll, Seungyoon Peter Song, Peter N. Glaskowsky, Yu Qing Cheng
  • Patent number: 7802073
    Abstract: The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: September 21, 2010
    Assignee: Oracle America, Inc.
    Inventors: Yu Qing Cheng, John Gregory Favor, Carlos Puchol, Seungyoon Peter Song, Peter Glaskowsky, Laurent Moll, Joe Rowlands, Donald Alpert
  • Patent number: 7797512
    Abstract: A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 14, 2010
    Assignee: Oracle America, Inc.
    Inventors: Yu Qing Cheng, John Gregory Favor, Peter N. Glaskowsky, Laurent R. Moll, Carlos Puchol, Seungyoon Peter Song
  • Publication number: 20090132764
    Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 21, 2009
    Applicant: Montalvo Systems, Inc.
    Inventors: Laurent R. MOLL, Seungyoon Peter SONG, Peter N. GLASKOWSKY, Yu Qing CHENG
  • Patent number: 7516274
    Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 7, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Laurent R. Moll, Seungyoon Peter Song, Peter N. Glaskowsky, Yu Qing Cheng