Abstract: A battery mounting structure for a vehicle is provided to include a case having a first internal member that is disposed to be spaced parallel to an upper side of a lower panel of the case and a second internal member that is disposed perpendicular to the first internal member, and configured to accommodate a plurality of battery modules therein using the first internal member and the second internal member. An outer side member is provided in a shape protruding toward the outside on an outer side of the case. The battery modules are disposed in a stacking direction of battery cells that is parallel to a longitudinal direction of the first internal member.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A semiconductor device includes a phase difference detection circuit configured to generate a detection signal by detecting a phase difference of a clock and a strobe signal, the detection signal being generated at a logic level of the strobe signal in synchronization with the clock, and configured to generate a write clock by delaying the strobe signal. The semiconductor device also includes a control signal generation circuit configured to store the detection signal, in synchronization with the write clock, and configured to output the stored detection signal as a control signal.

Abstract: A semiconductor device includes a data detection circuit configured to detect a number of bits having a predetermined logic level among bits included in data to generate a detection signal. The semiconductor device also includes a selection/transmission circuit configured to output the detection signal or a control data signal as a pre-masking signal based on a selection/transmission signal. The semiconductor device further includes a masking signal generation circuit configured to latch the pre-masking signal based on a pipe input control signal and configured to output the latched signal of the pre-masking signal as a masking signal for controlling a data masking operation based on a pipe output control signal.

Abstract: A semiconductor device includes a phase difference detection circuit configured to generate a detection signal by detecting a phase difference of a clock and a strobe signal, the detection signal being generated at a logic level of the strobe signal in synchronization with the clock, and configured to generate a write clock by delaying the strobe signal. The semiconductor device also includes a control signal generation circuit configured to store the detection signal, in synchronization with the write clock, and configured to output the stored detection signal as a control signal.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.

Abstract: A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A semiconductor memory device includes: a plurality of memory areas; a target area setting unit suitable for designating a target area according to a number of accesses to the respective memory areas; a random address generation unit suitable for generating a random address within the respective memory areas in a random manner; a target address generation unit suitable for generating a target address based on the target area and the random address; and a driving unit suitable for performing a smart refresh operation according to the target address.

Abstract: A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.

Abstract: A semiconductor memory device includes: a plurality of memory areas; a target area setting unit suitable for designating a target area according to a number of accesses to the respective memory areas; a random address generation unit suitable for generating a random address within the respective memory areas in a random manner; a target address generation unit suitable for generating a target address based on the target area and the random address; and a driving unit suitable for performing a smart refresh operation according to the target address.

Abstract: An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.

Abstract: A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.

Abstract: A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines, and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration exceeds a predetermined threshold.

Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.

Abstract: A semiconductor device includes a first pad suitable for receiving a first clock that is inputted from an exterior, a second pad suitable for receiving a second clock that is inputted from the exterior, a differential clock recognition unit suitable for recognizing between the first clock and the second clock as a positive clock of differential clocks and recognizing the other as a negative clock of the differential clocks in response to a mirror function signal which represents whether a mirror function is enabled or not, an output unit suitable for outputting an internal signal as an output signal in response to the differential clocks and controlling an output moment of the output signal in response to the mirror function signal and an output moment control signal, and a third pad suitable for supplying the output signal to the exterior.

Abstract: A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.

Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.