Patents by Inventor Yu-Ruei Chen

Yu-Ruei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Publication number: 20200212030
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 2, 2020
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10658241
    Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20200144483
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.
    Type: Application
    Filed: December 31, 2019
    Publication date: May 7, 2020
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20200144485
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20200123495
    Abstract: Described herein are methods and compositions for controlling insects and microorganims growth using Pseudomonas taiwanensis and its culture broth.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 23, 2020
    Inventors: Ming-Che Shih, Wen-Jen Chen, Je-Ruei Liu, Yu-Liang Yang
  • Publication number: 20200066704
    Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.
    Type: Application
    Filed: November 5, 2019
    Publication date: February 27, 2020
    Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Chin-Liang Chen, Jing Ruei Lu
  • Patent number: 10566520
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 10515941
    Abstract: Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Kuan-Lin Ho, Wei-ting Lin, Chin-Liang Chen, Jing Ruei Lu
  • Publication number: 20190378971
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Application
    Filed: July 8, 2018
    Publication date: December 12, 2019
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 10374006
    Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20190221544
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10355048
    Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20190181046
    Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20190074272
    Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.
    Type: Application
    Filed: October 31, 2018
    Publication date: March 7, 2019
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 10153265
    Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20170365675
    Abstract: A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 21, 2017
    Inventors: Ching-Yu Chang, Ying-Chiao Wang, Hon-Huei Liu, Jyh-Shyang Jenq, Chung-Liang Chu, Yu-Ruei Chen