Patents by Inventor Yu-Ruei Chen
Yu-Ruei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240128106Abstract: The invention discloses a container for a non-rectangular reticle, adapted for accommodating an elliptical reticle, and including a cover and a base which are configured to define an elliptical space when engaged with each other. The cover and the base have reticle retainers and reticle supports, respectively, which are configured to securely hold the elliptical reticle.Type: ApplicationFiled: September 21, 2023Publication date: April 18, 2024Inventors: Ming-Chien CHIU, Chia-Ho CHUANG, Hsin-Min HSUEH, Yu-Ruei CHEN
-
Publication number: 20240107895Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: ApplicationFiled: December 4, 2023Publication date: March 28, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
-
Patent number: 11935854Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.Type: GrantFiled: March 8, 2023Date of Patent: March 19, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
-
Patent number: 11877520Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: GrantFiled: February 9, 2023Date of Patent: January 16, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
-
Patent number: 11869953Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: GrantFiled: September 13, 2022Date of Patent: January 9, 2024Assignee: UNITED MICROELECTRONICS CORPInventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
-
Publication number: 20230326997Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.Type: ApplicationFiled: May 18, 2022Publication date: October 12, 2023Applicant: United Microelectronics Corp.Inventors: Jia-He Lin, Yu-Ruei Chen, Yu-Hsiang Lin
-
Patent number: 11721702Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: GrantFiled: June 20, 2022Date of Patent: August 8, 2023Assignee: United Microelectronics Corp.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
-
Publication number: 20230223366Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
-
Publication number: 20230207692Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
-
Publication number: 20230200256Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: ApplicationFiled: February 9, 2023Publication date: June 22, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
-
Patent number: 11640949Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.Type: GrantFiled: August 19, 2021Date of Patent: May 2, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
-
Publication number: 20230112835Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.Type: ApplicationFiled: December 7, 2022Publication date: April 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen
-
Patent number: 11626515Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.Type: GrantFiled: December 2, 2020Date of Patent: April 11, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
-
Patent number: 11611035Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: GrantFiled: February 22, 2021Date of Patent: March 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
-
Publication number: 20230008792Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.Type: ApplicationFiled: August 19, 2021Publication date: January 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
-
Patent number: 11552001Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.Type: GrantFiled: December 14, 2020Date of Patent: January 10, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen
-
Publication number: 20230006048Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Inventors: Sheng-Yao HUANG, Yu-Ruei CHEN, Zen-Jay TSAI, Yu-Hsiang LIN
-
Patent number: 11476343Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.Type: GrantFiled: March 26, 2021Date of Patent: October 18, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
-
Publication number: 20220320147Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: ApplicationFiled: June 20, 2022Publication date: October 6, 2022Applicant: United Microelectronics Corp.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
-
Patent number: 11417685Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.Type: GrantFiled: November 29, 2019Date of Patent: August 16, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin