Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.

Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a base portion and wherein the base portion includes a surface; performing a patterning step to form a plurality of protrusions, wherein the plurality of protrusions are arranged on the surface of the base portion; forming a buffer layer on the surface of the base portion by physical vapor deposition, wherein the buffer layer covers the protrusions; and forming III-V compound semiconductor layers on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; and wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.

Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.

Abstract: A method of cell placement includes choosing the ray-tracing channel matrices for the Nth iteration according to candidate cell locations of the Nth iteration and the user distributions, calculating fitness values for the Nth iteration based on the ray-tracing channel matrices, substituting the fitness values for the Nth iteration and corresponding candidate cell locations for the best fitness and best candidate cell locations in a total iterative process respectively if the fitness values for the Nth iteration are greater than or equal to multiple thresholds and the best fitness in a total iterative process, storing candidate cell locations of the Nth iteration, and verifies termination criteria, if termination criteria are not satisfied at the Nth iteration, generating the candidate cell locations of the N+1th iteration.

Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.

Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.

Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 ?m; wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.

Abstract: A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature.

Abstract: A semiconductor device includes a substrate, a conductive material, and a material layer. The substrate includes a through hole. The conductive material fills the through hole. The material layer is formed in the conductive material, wherein an electrical resistance of the conductive material is lower than an electrical resistance of the material layer.

Abstract: A through-silicon via (TSV) includes an insulation layer continuously lining a straight sidewall of a recessed via feature; a barrier layer continuously covering the insulation layer; a first portion of a non-continuous seed layer disposed at one end of the recessed via feature; a non-continuous dielectric layer partially covering the straight sidewall of the recessed via feature; and a conductive layer filling the recessed via feature.

Abstract: A method for fabricating a metal redistribution layer is described. A first opening and a second opening are formed in a dielectric layer over a first region and a second region thereof, respectively. A plurality of third openings are formed in the dielectric layer exposed by the first opening in the first region and a plurality of fourth openings are formed in the dielectric layer exposed by the second opening in the second region. A metal material is formed over the dielectric layer and in the first, second, third and fourth openings. A plurality of recesses is formed in the metal materials overlying the third and fourth openings. The metal material in the first region is patterned by using the recesses formed in portions of the metal material overlying the fourth openings in the second region as an alignment mark to form a metal redistribution layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.

Abstract: An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially.