Abstract: The present application provides a method for process a substrate. The method includes steps of providing a substrate having a sacrificial layer and an insulative layer, forming a polysilicon hardmask on the insulative layer, etching the insulative and sacrificial layers through multiple openings in the polysilicon hardmask to thus form multiple channels, depositing a metal film and a passivation film on the polysilicon hardmask and in the channels, performing a first removal process to remove portions of the passivation film and the metal film above the polysilicon hardmask, performing a second removal process to remove portions of the polysilicon hardmask exposed through the passivation film and the metal film, and performing a third removal process to remove the polysilicon hardmask and portions of the passivation film and the metal film surrounding the polysilicon is hardmask.

Abstract: The present application provides a method for manufacturing a capacitor array. The method includes steps of depositing a sacrificial layer on a bottom electrode; depositing an insulative layer on the sacrificial layer; forming a polysilicon hardmask on the insulative layer; etching the insulative layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hardmask to form channels; depositing a metal film on the polysilicon hardmask and in the channels; depositing a passivation film on the metal film; depositing a conductive material in the channels and in contact with the insulative layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulative layer.

Abstract: The present application provides a method for process a substrate. The method includes steps of providing a substrate having a sacrificial layer and an insulative layer, forming a polysilicon hardmask on the insulative layer, etching the insulative and sacrificial layers through multiple openings in the polysilicon hardmask to thus form multiple channels, depositing a metal film and a passivation film on the polysilicon hardmask and in the channels, performing a first removal process to remove portions of the passivation film and the metal film above the polysilicon hardmask, performing a second removal process to remove portions of the polysilicon hardmask exposed through the passivation film and the metal film, and performing a third removal process to remove the polysilicon hardmask and portions of the passivation film and the metal film surrounding the polysilicon is hardmask.

Abstract: The present application provides a method for manufacturing a capacitor array. The method includes steps of depositing a sacrificial layer on a bottom electrode; depositing an insulative layer on the sacrificial layer; forming a polysilicon hardmask on the insulative layer; etching the insulative layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hardmask to form channels; depositing a metal film on the polysilicon hardmask and in the channels; depositing a passivation film on the metal film; depositing a conductive material in the channels and in contact with the insulative layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulative layer.

Abstract: A testing apparatus, testing system, and non-transitory tangible machine-readable medium thereof are provided. The testing apparatus includes a first transmission interface, a second transmission interface, a storage, and a processor, wherein the processor is electrically connected to the first transmission interface, the second transmission interface, and the storage. The storage stores a test procedure, wherein the test procedure includes a test item. The storage also stores a piece of expected information corresponding to the test item. The processor reads the test item of the test procedure. The processor determines a test result of a touch mobile device regarding the test item according to the piece of expected information and at least one of a test datum received from the touch mobile device by the first transmission interface and a feedback signal received from a motor controller by the second transmission interface.

Abstract: Technologies described herein provide application autorouting for converting a data item into a new data format. Technologies described herein include determining a current data format of a data item and a desired data format of the data item. Additionally, technologies described herein further include determining, based at least partly on application information data associated with a plurality of applications, one or more applications of the plurality of applications that, based at least partly on executing the one or more applications in succession, convert the data item from the current data format to the desired data format. Furthermore, technologies described herein include sending the data item and a request to an application of the one or more applications to convert the data item from the current data format to a new data format and receiving a response to the request, the response including the data item in the new data format.

Abstract: An error correction method for a solid state storage device is provided. A controller of the solid state storage device issues plural slicing voltages to a flash memory. The flash memory issues a soft data to a soft decoder of the controller according to the plural slicing voltages. Firstly, the soft decoder receives the soft data, and performs an error correction process of the soft data according to a predetermined log-likelihood ratio (LLR) parameter set. If the error correction process of the soft data is not successfully completed according to the predetermined LLR parameter set, one LLR parameter set is selected from plural parameter sets of a LLR table and the error correction process of the soft data is performed according to the selected LLR parameter set.

Abstract: A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.

Abstract: A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.

Abstract: A solid state storage device and controlling method thereof are provided, and the method includes following steps. Data is programmed into a flash memory module by using a first programming scheme. A data error parameter of the flash memory module is determined. If the data error parameter is greater than an error predefine value, the data is programmed into the flash memory module by using a second programming scheme. The first programming scheme and the second programming scheme are respectively mapping to a first threshold voltage frame and a second threshold voltage frame, and voltage interval of the second threshold voltage frame is broader than voltage interval of the first threshold voltage frame.

Abstract: A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, MN ICI patterns are determined according to N neighboring cells having a significant ICI effect. If the central cell has a first storing state, MN central cell threshold voltage shifts corresponding to the MN ICI patterns are determined according to the voltage shift parameter table, and the first storing state is divided into plural sub-regions. Afterwards, the central cells corresponding to a first number of ICI patterns are classified into a first group of the first storing state. The central cell threshold voltage shifts corresponding to the first number of ICI patterns lie in a first sub-region of the first storing state.

Abstract: The present invention relates to a cryopreservative device comprising an outer case, one or more layers of space for the cryo-bags, and two or more Teflon cryopreservative bags. The outer case has a cover lip for opening and closing. The Teflon cryopreservative bags are filled with a freezing resistant. In the present invention, the cryo-bags and the Teflon cryopreservative bags are crossly stacked in the cryopreservation device. The Teflon cryopreservative bags are designed to directly contact with the cryo-bags in order to obtain the effect of slow cell freezing.

Abstract: A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, MN ICI patterns are determined according to N neighboring cells having a significant ICI effect. If the central cell has a first storing state, MN central cell threshold voltage shifts corresponding to the MN ICI patterns are determined according to the voltage shift parameter table, and the first storing state is divided into plural sub-regions. Afterwards, the central cells corresponding to a first number of ICI patterns are classified into a first group of the first storing state. The central cell threshold voltage shifts corresponding to the first number of ICI patterns lie in a first sub-region of the first storing state.

Abstract: The present invention pertains to a light emitting diode with high luminance and method therefor, and specially to a light emitting diode having a selectively highly-doped low resistive layer of InGaAlP. The selectively highly-doped low resistive layer may be grown by the current epitaxy technique. Therefore, the light emitting diode of the present application may be mass produced, thus having industrial applicability.