Abstract: A device includes a first cell active area asymmetrically positioned in a first device column between a first barrier line and a second barrier line, a second cell active area asymmetrically positioned in a second device column between the first barrier line and a third barrier line, where the first cell has a first cell length in a first direction perpendicular to the first barrier line which is three times a second cell length in the first direction. The first cell active area and the second cell active area are a first distance from the first barrier line, and the first cell active area is a second distance from the second barrier line, and the second cell active area is the second distance away from the third barrier line.

Abstract: In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A signal receiving apparatus is provided. A time de-interleaver performs time de-interleaving on multiple interleaved video frames to generate a time de-interleaving result, and generates a counting request upon identifying a starting point of an interleaved video frame under verification. A signal processing circuit performs signal processing having an average delay on the time de-interleaving result to generate a signal processing result. A de-jittering buffer generates an output request upon obtaining an original time-to-output (TTO) of the interleaved video frame under verification, and transforms the signal processing result to a transport stream. A verification circuit generates a counting result according to the counting request and the output request, and determines whether the TTO satisfies a predetermined condition according to the counting result and the average delay.

Abstract: A roll-off parameter determining module disposed at a receiving terminal is provided. The receiving terminal receives first roll-off information of a first frame and second roll-off information of a second frame. The first frame is adjacent to the second frame. The module for determining a roll-off parameter includes: a register unit; a first determining unit, determining whether one of the first roll-off information and the second roll-off information includes a first data type, and generating a first roll-off parameter indicator; a second determining unit, determining whether one of the first roll-off information and the second roll-off information includes a second data type and outputting a second roll-off parameter indicator; and a look-up table (LUT) unit, looking up an LUT according to the first roll-off parameter indicator and a second roll-off parameter indicator to output a roll-off parameter.

Abstract: A roll-off parameter determining module disposed at a receiving terminal is provided. The receiving terminal receives first roll-off information of a first frame and second roll-off information of a second frame. The first frame is adjacent to the second frame. The module for determining a roll-off parameter includes: a register unit; a first determining unit, determining whether one of the first roll-off information and the second roll-off information includes a first data type, and generating a first roll-off parameter indicator; a second determining unit, determining whether one of the first roll-off information and the second roll-off information includes a second data type and outputting a second roll-off parameter indicator; and a look-up table (LUT) unit, looking up an LUT according to the first roll-off parameter indicator and a second roll-off parameter indicator to output a roll-off parameter.

Abstract: A time-domain equalizer includes a delay circuit, a weighting circuit, a controller and a summation circuit. The delay circuit receives an equalized signal and accordingly generates M delayed signals for an equalized signal. The weighting circuit applies an mth weighting of M weightings to an mth delayed signal of the M delayed signals to generate an mth weighted signal. The summation circuit sums up the M weighted signals, according to which the equalized signal is updated. The controller iteratively updates the M weightings according to a vector {right arrow over (e)}n,p=[en,p,1 . . . en,p,M], where the symbol en,p,j is defined as en,p,j=?k(z[k]*z[k?Dp,j]*), the symbol n is an iteration index, k is a sample index, z[k] is a kth sample of the equalized signal, j is an integer index between 1 and M, and Dp,j represents a time delay amount corresponding to a jth delayed signal of the M delayed signals.

Abstract: A time-domain equalizer includes a delay circuit, a weighting circuit, a controller and a summation circuit. The delay circuit receives an equalized signal and accordingly generates M delayed signals for an equalized signal. The weighting circuit applies an mth weighting of M weightings to an mth delayed signal of the M delayed signals to generate an mth weighted signal. The summation circuit sums up the M weighted signals, according to which the equalized signal is updated. The controller iteratively updates the M weightings according to a vector n,p=[en,p,1 . . . en,p,M], where the symbol en,p,j is defined as en,p,j=?k(z[k]*z[k?Dp,j]*) the symbol n is an iteration index, k is a sample index, z[k] is a kth sample of the equalized signal, j is an integer index between 1 and M, and Dp,j represents a time delay amount corresponding to a jth delayed signal of the M delayed signals.

Abstract: A data processing circuit for performing a de-interleaving process in a DVB-T2 system is provided. The data processing circuit includes: a buffer, buffering a plurality of data symbols; a memory, coupled to the buffer; an address generator, generating a plurality of addresses according to an operation logic and a permutation rule, and selecting and outputting a target address from the addresses; and a memory controller, coupled to the memory, the buffer and the address generator, writing the target data into the memory according to the target address, or/and reading the target data from the memory according to the target address, until the data symbols are de-interleaved when the data symbols are read from the memory.

Abstract: A multimedia processing system for processing a plurality of transport streams of different digital video broadcasting standards includes: a configuration module, generating a control signal; a descrambler, receiving a single transport stream and the control signal to generate header information, data information and padding information; a data processing module, generating an input stream synchronization signal and transport stream packet processed information according to the output of the descrambler; a timing control module, receiving the padding information, the input transport stream synchronization signal and the control signal to generate a time-to-output signal and a packet interval signal; and an output module, receiving the time-to-output signal, the packet interval signal, the transport stream packet processed information and the control signal to generate output stream information.

Abstract: A time-domain equalizer for eliminating an echo signal from a received signal is provided. The received signal includes an original signal and the echo signal. The time-domain equalizer includes a time delay estimator, an amplitude amplifying ratio estimator and a phase shift estimator. The time delay estimator determines a delay amount maximizing a cost function to serve as an estimated delay amount of the echo signal relative to the original signal. The amplitude amplifying ratio estimator determines an estimated amplitude amplifying ratio of the echo signal relative to the original signal. The phase shift estimator determines an estimated phase shift of the echo signal relative to the original signal according to the estimated delay amount. The estimated delay amount, the estimated amplitude amplifying ratio and the estimated phase shift are used to set a filtering condition to be applied to the received signal.

Abstract: A data processing circuit for performing a de-interleaving process in a DVB-T2 system is provided. The data processing circuit includes: a buffer, buffering a plurality of data symbols; a memory, coupled to the buffer; an address generator, generating a plurality of addresses according to an operation logic and a permutation rule, and selecting and outputting a target address from the addresses; and a memory controller, coupled to the memory, the buffer and the address generator, writing the target data into the memory according to the target address, or/and reading the target data from the memory according to the target address, until the data symbols are de-interleaved when the data symbols are read from the memory.

Abstract: A High Definition (HD) video wireless transmission method for transmitting a data packet for a video frame of an HD video is provided. The method includes: receiving the video frame which comprises a video frame size; acquiring a payload length and a Minimal Required Transmission Time (MRTT) associated with the video frame, wherein the MRTT is a minimal time bound for transmitting the video frame to a receiving end; performing partitioning to the video frame for acquiring the data packet according to the payload length; and performing scheduling to the data packet according to the MRTT, and the scheduled data packet is transmitted to the receiving end.

Abstract: A cooperative apparatus and a resource block allocation method thereof for use in a wireless network are provided. The wireless network comprises a plurality of femtocells. The cooperative apparatus groups the femtocells based on signal interferences between the femtocells. The femtocells with higher signal interferences are joined to the same femtocell group. The cooperative apparatus averagely allocates resource blocks to the femtocells in the same femtocell group, and randomly allocates resource blocks to different femtocell groups.

Abstract: A High Definition (HD) video wireless transmission method for transmitting a data packet for a video frame of an HD video is provided. The method includes: receiving the video frame which comprises a video frame size; acquiring a payload length and a Minimal Required Transmission Time (MRTT) associated with the video frame, wherein the MRTT is a minimal time bound for transmitting the video frame to a receiving end; performing partitioning to the video frame for acquiring the data packet according to the payload length; and performing scheduling to the data packet according to the MRTT, and the scheduled data packet is transmitted to the receiving end.

Abstract: A cooperative apparatus and a resource block allocation method thereof for use in a wireless network are provided. The wireless network comprises a plurality of femtocells. The cooperative apparatus groups the femtocells based on signal interferences between the femtocells. The femtocells with higher signal interferences are joined to the same femtocell group. The cooperative apparatus averagely allocates resource blocks to the femtocells in the same femtocell group, and randomly allocates resource blocks to different femtocell groups.

Abstract: A femtocell and a resource allocation method thereof are provided. The femtocell comprises a storage unit and a processing unit. The storage unit is configured to store a priority region threshold. The processing unit is configured to assign a first region of a frame as a CSG region according to a priority region threshold and assign a second region of the frame as a non-CSG region according to the priority region threshold. The CSG region and the non-CSG region are exclusive.