Abstract: A high-speed data transmission structure includes first and second electronic units and an input/output bus. The input/output bus is electrically connected to the first and second electronic units, and includes a clock signal line and N data lines, where N is an even integer. The data lines are divided into first and second data signal line groups, each provided with the same number of data lines. In a transmit mode, the first electronic unit generates and transmits a clock signal to the clock data line, and generates output signals at each clock period of the clock signal. The output signals consist of N/2 data signals lasting for two clock periods of the clock signal, and the first and second data signal line groups alternatively receive the output signals. The second electronic unit simultaneously performs a receive mode to fetch and latch the data signals according to the clock signal.