Abstract: A dielectric barrier sidewall protected via in combination with a conventional metal barrier is integrated in a dual damascene process. Via reliability, copper filling ability and copper CMP uniformity will be significantly improved according to this invention.

Abstract: A conducting layer is formed on a substrate and a first passivation layer is formed on the conducting layer. Following this, a first photo-chemical low dielectric constant (low-k) layer, a second passivation layer and a second low-k photo-chemical layer are formed in order on the substrate. Then, a first photolithographic process is performed to form a trench in the second low-k photo-chemical dielectric layer. A first etching process is performed to remove portions of the second passivation layer not covered by the second low-k photo-chemical layer down to the surface of the first low-k photo-chemical layer. Subsequently, a second photolithographic process is performed to form a via hole in the first low-k photo-chemical layer. Finally, a second etching process is performed to remove portions of the first passivation layer not covered by the first low-k photo-chemical layer down to the surface of the conducting layer.