Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: Provided is an electronic device including a first liquid crystal layer having a first side and a second side opposite thereto; a second liquid crystal layer disposed on the first liquid crystal layer and having a third side and a fourth side opposite thereto; a first alignment layer disposed on the first side and having a first alignment direction; a second alignment layer disposed on the second side and having a second alignment direction opposite to the first alignment direction; a third alignment layer disposed on the third side and having a third alignment direction; and a fourth alignment layer disposed on the fourth side and having a fourth alignment direction opposite to the third alignment direction. The second alignment layer is between the first liquid crystal layer and the third alignment layer. The third alignment layer is between the second liquid crystal layer and the second alignment layer.

Abstract: Provided is an electronic device including a first liquid crystal layer having a first side and a second side opposite thereto; a second liquid crystal layer disposed on the first liquid crystal layer and having a third side and a fourth side opposite thereto; a first alignment layer disposed on the first side and having a first alignment direction; a second alignment layer disposed on the second side and having a second alignment direction opposite to the first alignment direction; a third alignment layer disposed on the third side and having a third alignment direction; and a fourth alignment layer disposed on the fourth side and having a fourth alignment direction opposite to the third alignment direction. The second alignment layer is between the first liquid crystal layer and the third alignment layer. The third alignment layer is between the second liquid crystal layer and the second alignment layer.

Abstract: A data inspection system includes: a communication circuit arranged to operably communicate data with a plurality of attributes filtering devices to receive multiple activity records which are generated by the plurality of attributes filtering devices and corresponding to multiple IoT devices in a plurality of target IoT systems; a storage circuit arranged to operably store the multiple activity records received by the communication circuit; and a data classification circuit coupled with the storage circuit and arranged to operably classify each of the multiple activity records received by the communication circuit based on N attributes to form M data groups; wherein N is 2 or an integer greater than 2, while M is at least two times of N.

Abstract: A data inspection system includes: a communication circuit arranged to operably communicate data with a plurality of attributes filtering devices to receive multiple activity records which are generated by the plurality of attributes filtering devices and corresponding to multiple IoT devices in a plurality of target IoT systems; a storage circuit arranged to operably store the multiple activity records received by the communication circuit; and a data classification circuit coupled with the storage circuit and arranged to operably classify each of the multiple activity records received by the communication circuit based on N attributes to form M data groups; wherein N is 2 or an integer greater than 2, while M is at least two times of N.

Abstract: An Internet of Things (IoT) operations monitoring system includes: a plurality of attributes filtering devices for generating multiple activity records respectively corresponding to multiple IoT devices in a plurality of target IoT systems; and a data inspection system which includes: a communication circuit arranged to operably communicate data with the plurality of attributes filtering devices to receive the multiple activity records; a storage circuit arranged to operably store the multiple activity records received by the communication circuit; and a data classification circuit coupled with the storage circuit and arranged to operably classify each of the multiple activity records received by the communication circuit based on N attributes to form M data groups; wherein N is 2 or an integer greater than 2, while M is at least two times of N.

Abstract: An electronic device is provided, which includes a first phase retardation element, a second phase retardation element and a liquid-crystal layer. The second phase retardation element is disposed on the first phase retardation element, and the liquid-crystal layer is disposed between the first phase retardation element and the second phase retardation element. In addition, the liquid-crystal layer includes a chiral agent, and a pitch of the chiral agent is between 7 ?m and 25 ?m. The first phase retardation element has a first in-plane retardation value and a first out-plane retardation value, and the second phase retardation element has a second in-plane retardation value and a second out-plane retardation value. The first in-plane retardation value and the second in-plane retardation value are between 20 nanometers and 70 nanometers, and the first out-plane retardation value and the second out-plane retardation value are between 170 nanometers and 210 nanometers.

Abstract: A display panel includes a first substrate, a second substrate, a display medium layer disposed between the first substrate and the second substrate, a first metal layer, a first insulation layer disposed on the first metal layer, a second metal layer, a second insulation layer disposed on the second metal layer, a pixel electrode layer and an intervening layer. The first metal layer is disposed on the first substrate to form a signal wiring and a gate. The second metal layer is disposed on the first insulation layer to form a data wiring, a source and a drain. The intervening layer is a patterned layer and disposed between the second insulation layer and the pixel electrode layer. The pixel electrode layer covers the intervening layer and the second insulation layer, and the perimeter of the intervening layer of a sub-pixel ranges between 500 ?m and 30000 ?m.

Abstract: The disclosure provides a display device. The pixel electrode of the display device includes a first pixel electrode and a second pixel electrode having the same electric potential. The first interlayer is formed between the first substrate and the first pixel electrode. Adjacent two of the first strip-shaped branches of the first interlayer form a first gap to expose part of the first substrate. The common electrode layer is disposed over the second substrate. The pixel electrode is positioned between the first substrate and the display medium layer. The first pixel electrode extends to cover the first gap. A difference between a maximum distance between the first pixel electrode and the common electrode layer and a maximum distance between the second pixel electrode and the common electrode layer is 0.1 ?m to 0.4 ?m.

Abstract: A liquid-crystal display includes a first substrate including several sub-pixels. A micro-structure layer is formed on the first substrate, and the micro-structure layer corresponding to one of the sub-pixels includes a first main trunk portion, a second main trunk portion crossed the first main trunk portion, and several striped branch portions. The striped branch portions are connected with the first and second main trunk portions, wherein an angle is formed between the striped branch portions and the first main trunk portion, and the striped branch portions are alternately arranged with a pitch. A first electrode layer is conformally formed on the micro-structure layer. Specifically, the pitch in one of the sub-pixels is different from the pitch in another one of the sub-pixels, or the angle in one of the sub-pixels is different from the angle in another one of the sub-pixels.

Abstract: The disclosure provides a display device. The pixel electrode of the display device includes a first pixel electrode and a second pixel electrode having the same electric potential. The first interlayer is formed between the first substrate and the first pixel electrode. Adjacent two of the first strip-shaped branches of the first interlayer form a first gap to expose part of the first substrate. The common electrode layer is disposed over the second substrate. The pixel electrode is positioned between the first substrate and the display medium layer. The first pixel electrode extends to cover the first gap. A difference between a maximum distance between the first pixel electrode and the common electrode layer and a maximum distance between the second pixel electrode and the common electrode layer is 0.1 ?m to 0.4 ?m.

Abstract: A liquid-crystal display includes a first substrate including several sub-pixels. A micro-structure layer is formed on the first substrate, and the micro-structure layer corresponding to one of the sub-pixels includes a first main trunk portion, a second main trunk portion crossed the first main trunk portion, and several striped branch portions. The striped branch portions are connected with the first and second main trunk portions, wherein an angle is formed between the striped branch portions and the first main trunk portion, and the striped branch portions are alternately arranged with a pitch. A first electrode layer is conformally formed on the micro-structure layer. Specifically, the pitch in one of the sub-pixels is different from the pitch in another one of the sub-pixels, or the angle in one of the sub-pixels is different from the angle in another one of the sub-pixels.

Abstract: A display panel includes a first substrate, a second substrate, a display medium layer disposed between the first substrate and the second substrate, a first metal layer, a first insulation layer disposed on the first metal layer, a second metal layer, a second insulation layer disposed on the second metal layer, a pixel electrode layer and an intervening layer. The first metal layer is disposed on the first substrate to form a signal wiring and a gate. The second metal layer is disposed on the first insulation layer to form a data wiring, a source and a drain. The intervening layer is a patterned layer and disposed between the second insulation layer and the pixel electrode layer. The pixel electrode layer covers the intervening layer and the second insulation layer, and the perimeter of the intervening layer of a sub-pixel ranges between 500 ?m and 30000 ?m.

Abstract: A multimedia file storage system, a related source-end device and a destination-end device are disclosed. The source-end device includes a source-end storage device for storing an original multimedia file; a source-end decoding circuit for decoding only a part of multiple B-pictures of the original multimedia file to form a source-end representative file; a source-end computing circuit for conducting a Hash algorithm computation based on the source-end representative file to generate a source-end check value; and a transmitting circuit for transmitting the source-end check value and the original multimedia file.

Abstract: The present invention relates to a pixel electrode structure, comprising: at least one scanning line disposed on a substrate; at least one data line disposed on the substrate and intersecting the scanning line to define a pixel area; a pixel electrode disposed in the pixel area; an active element comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is electrically connected to the scanning line, the source electrode is electrically connected to the data line, and the drain electrode is electrically connected to the pixel electrode; and a shielding electrode overlapping one side of the scanning line and electrically connected to the pixel electrode with a first connecting part, wherein the shielding electrode has a jag structure, and the first connecting part is disposed at a junction between jags of the jag structure protruding in different orientations.

Abstract: A multimedia storage system includes a multimedia distribution device and a plurality of storage devices. The multimedia distribution device splits a multimedia file into a plurality of multimedia segments and monitors the operation statuses of the storage devices. The multimedia distribution device further configures each of the multimedia segments to be stored in at least two of the storage devices according to the available storage devices in the multimedia storage system. The storage device comprises a network access device for receiving the multimedia segments and a redundant array of inexpensive disks for storing the received multimedia segments.

Abstract: The present invention relates to a pixel electrode structure, comprising: at least one scanning line disposed on a substrate; at least one data line disposed on the substrate and intersecting the scanning line to define a pixel area; a pixel electrode disposed in the pixel area; an active element comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is electrically connected to the scanning line, the source electrode is electrically connected to the data line, and the drain electrode is electrically connected to the pixel electrode; and a shielding electrode overlapping one side of the scanning line and electrically connected to the pixel electrode with a first connecting part, wherein the shielding electrode has a jag structure, and the first connecting part is disposed at a junction between jags of the jag structure protruding in different orientations.

Abstract: An energy-saving heat exchanger for a VOC abatement system. The energy-saving heat exchanger includes a fresh air chamber for receiving fresh air from a blower; a heated air chamber for receiving heated air from a secondary heat exchanger of the VOC abatement system; a mixed air chamber provided at the outlet ends of the fresh air chamber and heated air chamber; and a heat exchange chamber leading from the heated air chamber and disposed in thermally-conductive contact with the fresh air chamber. An oxygen detector measures the oxygen composition of air flowing from the mixed air chamber and operates a damper which controls flow of air from the heated air chamber to the mixing chamber.