Patents by Inventor Yu-Sheng Lai

Yu-Sheng Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121685
    Abstract: A method of reducing gray energy consumption and achieving optimal gray energy saving for carbon neutralization is proposed. In a cellular network, each cell or BS (group of cells) has renewable (green) and non-renewable (gray, on-grid power) energy sources. The renewable (green) energy is highly variable and unpredictable, while non-renewable (gray, on-grid power) is stable but is not renewable and thus has more carbon impact. Each cell or BS (group of cells) services is associated UEs when it is on. In one novel aspect, a cell or BS (group of cells) that consumes more non-renewable energy can give some or all of its served UEs to another cell or BS (group of cells) that consumes less non-renewable energy.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 11, 2024
    Inventors: Chien-Sheng Yang, I-Kang Fu, YUAN-CHIEH LIN, Chia-Lin Lai, Yu-Hsin Lin, Yun-Hsuan Chang
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Patent number: 11915991
    Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Publication number: 20230376090
    Abstract: An electronic device with movable foot pad, including a body and a foot pad module, is provided. The body has a bottom surface. The foot pad module includes a first foot pad, at least one second foot pad, and at least one rotating shaft connecting the first and second foot pads. The second foot pad is rotated relative to the first foot pad by the rotating shaft to switch the foot pad module between first and second states. An axial direction of the rotating shaft is inclined relative to the bottom surface. In the first state, the body is supported on the platform by the first and second foot pads. In the second state, the second foot pad is rotated 180 degrees relative to the first foot pad in the axial direction and protrudes from the first foot pad to support the body on the platform by the second foot pad.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 23, 2023
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: I-Hsuan Tsai, Chia-Wei Chen, Yu-Sheng Lai, Tzu-Chien Lai
  • Patent number: 11415457
    Abstract: The present invention provides a vibration sensor, which comprises a circuit board having an accommodating space. A sensing assembly is disposed in the accommodating space. A recess for magnet sliding is disposed in the sensing assembly. Dispose a magnet in the recess and then dispose a coil layer on an arbitrary side or both sides of the sensing assembly. Furthermore, a lubricating layer is coated on the recess. Alternatively, the recess can be a vacuum structure or a hollow cross-sectional structure for reducing the friction between the recess and the magnet. Alternatively, the coil layer can be coated with a protective layer or multiple layers can be stacked. Without increasing the area of the sensor, the sensing on the variation of magnetic flux can be improved. Accordingly, the vibration sensor according to the present invention can achieve wideband detection of vibrations.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 16, 2022
    Assignee: National Applied Research Laboratories
    Inventors: Yu-Sheng Lai, Jui-Min Liu, Hsu-Chun Cheng, Mei-I Li, Chun-Chi Chen, Cheng-San Wu, Jia-Min Shieh
  • Publication number: 20220176504
    Abstract: A method for adjusting a workpiece-supporting module includes: setting initial support position information of a workpiece, the initial support position information including positions of support devices and a spacing value for separating the support devices; according to the initial support position information, applying a finite element method to analyze a CAD file of the workpiece to obtain workpiece deformation information; according to the workpiece deformation information and target workpiece deformation information, realizing support position information corresponding to each support device, the support position information including X-axis coordinates and Y-axis coordinates; according to the support position information and a conversion program, obtaining a Z-axis coordinate and a normal vector of each support devices; and, according to the support position information, the Z-axis coordinate and the normal vector, adjusting the position and the angle of each support device.
    Type: Application
    Filed: April 8, 2021
    Publication date: June 9, 2022
    Inventors: CHUN-TING CHEN, CHIEN-CHIH LIAO, PEI-YIN CHEN, JEN-JI WANG, YU-SHENG LAI
  • Publication number: 20210026322
    Abstract: A detection device for a spindle of a machine tool is provided, wherein the spindle includes an insertion hole. The detection device includes a contact housing, a main housing, a sensor, and a process module. The contact housing has a first chamber, and the first chamber has an inner surface. The main housing is connected to the contact housing, and has a second chamber communicated with the first chamber. The sensor is disposed in the first chamber and connected to the inner surface. The process module is disposed in the second chamber and electrically connected to the sensor. When the contact housing is inserted into the insertion hole of the spindle, the sensor is configured to detect the deformation of the contact housing and generate a detection signal. The process module generates a determination signal according to the detection signal.
    Type: Application
    Filed: November 22, 2019
    Publication date: January 28, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Ming MA, Yu-Sheng LAI, Wei-Jen WU, Ta-Jen PENG, Tzuo-Liang LUO
  • Publication number: 20190360859
    Abstract: The present invention provides a vibration sensor, which comprises a circuit board having an accommodating space. A sensing assembly is disposed in the accommodating space. A recess for magnet sliding is disposed in the sensing assembly. Dispose a magnet in the recess and then dispose a coil layer on an arbitrary side or both sides of the sensing assembly. Furthermore, a lubricating layer is coated on the recess. Alternatively, the recess can be a vacuum structure or a hollow cross-sectional structure for reducing the friction between the recess and the magnet. Alternatively, the coil layer can be coated with a protective layer or multiple layers can be stacked. Without increasing the area of the sensor, the sensing on the variation of magnetic flux can be improved. Accordingly, the vibration sensor according to the present invention can achieve wideband detection of vibrations.
    Type: Application
    Filed: October 25, 2018
    Publication date: November 28, 2019
    Inventors: YU-SHENG LAI, JUI-MIN LIU, HSU-CHUN CHENG, MEI-I LI, CHUN-CHI CHEN, CHENG-SAN WU, JIA-MIN SHIEH
  • Patent number: 10180509
    Abstract: An environment monitoring system is utilized for monitoring an environmental variation status of a riverbed, a lake floor, or a seabed. The environment monitor system includes a wire drawing device configured at a monitoring point for releasing and tightening a transmission wire; a fixing pipe laid between the monitoring point and a structure layer for containing the transmission wire; a plurality of vibration sensing devices respectively configured on the transmission wire for converting sensed vibration energy to a plurality of electric signals and transmitting the plurality of electric signals by the transmission wire; an analyzing device coupled with the wire drawing device and the transmission wire for obtaining a released length of the transmission wire by the wire drawing device and determining the environmental variation status according to the released length and the plurality of electric signals to perform monitoring.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: January 15, 2019
    Assignee: National Applied Research Laboratories
    Inventors: Yung-Bin Lin, Yu-Sheng Lai, Meng-Huang Gu, Ho-Min Chang, Kuo-Chun Chang, Yuan-Chen Liao, Yung-Kang Wang, Mei-Yi Li, Cheng-San Wu, Wen-Kuan Yeh
  • Publication number: 20160154128
    Abstract: An environment monitoring system is utilized for monitoring an environmental variation status of a riverbed, a lake floor, or a seabed. The environment monitor system includes a wire drawing device configured at a monitoring point for releasing and tightening a transmission wire; a fixing pipe laid between the monitoring point and a structure layer for containing the transmission wire; a plurality of vibration sensing devices respectively configured on the transmission wire for converting sensed vibration energy to a plurality of electric signals and transmitting the plurality of electric signals by the transmission wire; an analyzing device coupled with the wire drawing device and the transmission wire for obtaining a released length of the transmission wire by the wire drawing device and determining the environmental variation status according to the released length and the plurality of electric signals to perform monitoring.
    Type: Application
    Filed: October 6, 2015
    Publication date: June 2, 2016
    Inventors: Yung-Bin Lin, Yu-Sheng Lai, Meng-Huang Gu, Ho-Min Chang, Kuo-Chun Chang, Yuan-Chen Liao, Yung-Kang Wang, Mei-Yi Li, Cheng-San Wu, Wen-Kuan Yeh
  • Publication number: 20150228837
    Abstract: The present invention provides a photodetector, which comprises a semiconductor substrate and a light absorbing layer (including metal layer, silicide layer) and the opening structures. In addition, a method of fabricating the abovementioned photodetector is also disclosed in the present invention.
    Type: Application
    Filed: February 9, 2015
    Publication date: August 13, 2015
    Inventors: Hsuen-Li CHEN, Keng-Te LIN, Yu-Sheng LAI, Chen-Chieh YU
  • Patent number: 8921075
    Abstract: A method of manufacturing a nanoparticle chain is disclosed. The method comprises the steps of: providing a single-stranded circular primer with a determined length, and amplifying the single-stranded circular primer into single-stranded DNA nanotemplate by an isothermal nucleotide amplification reaction such that an end of the single-stranded DNA nanotemplate is fixed to a surface of a substrate; and adding a single-stranded DNA probe conjugated with nanoparticle at one end of which, and attaching the single-stranded DNA probe to the corresponding sequence on the single-stranded DNA nanotemplate to form a nanoparticles chain. The method of manufacturing a nanoparticle chain further comprises providing a fluid, and the flowing direction of the fluid controls the aligning direction of the nanoparticle chain. Wherein, the inter-nanoparticle distance of the nanoparticle chain can be adjusted by adjusting a reaction temperature or adding the single-stranded DNA probe without conjugating with nanoparticles.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: December 30, 2014
    Assignee: National Applied Research Laboratories
    Inventors: Yen-Pei Lu, Ming-Yu Lin, Yu-Sheng Lai, Yuh-Shyong Yang, Hsuen-Li Chen, Yu-Cheng Ou
  • Patent number: 8773089
    Abstract: A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: July 8, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Yu-Sheng Lai, Feng-Chia Chang, Yu-Chou Ke
  • Publication number: 20140184939
    Abstract: A touch structure is provided. The touch structure includes a first sensing electrode, a second sensing electrode, a first dummy pattern and a second dummy pattern. The first sensing electrode and the second sensing electrode are arranged in a staggered manner and electrically insulated from each other. The first dummy pattern is adjacent to the first sensing electrode and has a first pattern acute angle. The second dummy pattern is adjacent to the second sensing electrode and has a second pattern acute angle. The first dummy pattern and the second dummy pattern are separated from each other. The first pattern acute angle and the second pattern acute angle are faced toward the same overlapped portion between the first sensing electrode and the second sensing electrode substantially.
    Type: Application
    Filed: July 17, 2013
    Publication date: July 3, 2014
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chih-Chang LAI, Chi-Te LIN, Tien-Nan WANG, He-Wei HUANG, Yu-Sheng LAI
  • Patent number: 8603882
    Abstract: A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: December 10, 2013
    Assignee: National Applied Research Laboratories
    Inventors: Szu-Hung Chen, Hung-Min Chen, Yu-Sheng Lai, Wen-Fa Wu, Fu-Liang Yang
  • Publication number: 20130273610
    Abstract: A method of manufacturing a nanoparticle chain is disclosed. The method comprises the steps of: providing a single-stranded circular primer with a determined length, and amplifying the single-stranded circular primer into single-stranded DNA nanotemplate by an isothermal nucleotide amplification reaction such that an end of the single-stranded DNA nanotemplate is fixed to a surface of a substrate; and adding a single-stranded DNA probe conjugated with nanoparticle at one end of which, and attaching the single-stranded DNA probe to the corresponding sequence on the single-stranded DNA nanotemplate to form a nanoparticles chain. The method of manufacturing a nanoparticle chain further comprises providing a fluid, and the flowing direction of the fluid controls the aligning direction of the nanoparticle chain. Wherein, the inter-nanoparticle distance of the nanoparticle chain can be adjusted by adjusting a reaction temperature or adding the single-stranded DNA probe without conjugating with nanoparticles.
    Type: Application
    Filed: June 5, 2012
    Publication date: October 17, 2013
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Yen-Pei Lu, Ming-Yu Lin, Yu-Sheng Lai, Yuh-Shyong Yang, Hsuen-Li Chen, Yu-Cheng Ou
  • Patent number: 8384454
    Abstract: A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: February 26, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Yu-Sheng Lai, Feng-Chia Chang, Chun Shiah
  • Patent number: 8330513
    Abstract: A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Etron Technology, Inc.
    Inventors: Yu-Sheng Lai, Feng-Chia Chang
  • Publication number: 20120229106
    Abstract: A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.
    Type: Application
    Filed: May 3, 2011
    Publication date: September 13, 2012
    Inventors: Yu-Sheng Lai, Feng-Chia Chang, Yu-Chou Ke
  • Publication number: 20120190163
    Abstract: A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
    Type: Application
    Filed: May 13, 2011
    Publication date: July 26, 2012
    Applicant: National Applied Research Laboratories
    Inventors: Szu-Hung Chen, Hung-Min Chen, Yu-Sheng Lai, Wen-Fa Wu, Fu-Liang Yang