Patents by Inventor Yu-Sheng Wang

Yu-Sheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220176504
    Abstract: A method for adjusting a workpiece-supporting module includes: setting initial support position information of a workpiece, the initial support position information including positions of support devices and a spacing value for separating the support devices; according to the initial support position information, applying a finite element method to analyze a CAD file of the workpiece to obtain workpiece deformation information; according to the workpiece deformation information and target workpiece deformation information, realizing support position information corresponding to each support device, the support position information including X-axis coordinates and Y-axis coordinates; according to the support position information and a conversion program, obtaining a Z-axis coordinate and a normal vector of each support devices; and, according to the support position information, the Z-axis coordinate and the normal vector, adjusting the position and the angle of each support device.
    Type: Application
    Filed: April 8, 2021
    Publication date: June 9, 2022
    Inventors: CHUN-TING CHEN, CHIEN-CHIH LIAO, PEI-YIN CHEN, JEN-JI WANG, YU-SHENG LAI
  • Patent number: 11355399
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Fu-Sheng Li, Tsai-Jung Ho, Bor Chiuan Hsieh, Guan-Xuan Chen, Guan-Ren Wang
  • Patent number: 11339267
    Abstract: Green, fast and easy evaporating organic solvent for use as a lubricant in the processing of polytetrafluoroethylene (PTFE) and expanded polytetrafluoroethylene (ePTFE) products and processes of using the solvents to fabricate the products are disclosed herein. The products can be used in the field of bio- and medical applications, such as for use in vascular grafts, cardiovascular and soft tissue patches, facial implants, surgical sutures, and endovascular prosthesis, and for any products known in the aerospace, electronics, fabrics, filtration, industrial and sealant arts.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 24, 2022
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Lih-Sheng Turng, Yiyang Xu, Yu-Jyun Lin, Dong-Fang Wang
  • Patent number: 11336215
    Abstract: A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 17, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Tai-Jung Huang, Pei-Chin Wang, Chien-Sheng Lo, Yu-Lin Fang, Yu-Ting Tsai
  • Publication number: 20220084879
    Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Inventors: Pei-Wen WU, Chun-I TSAI, Chi-Cheng HUNG, Jyh-Cherng SHEU, Yu-Sheng WANG, Ming-Hsing TSAI
  • Patent number: 11271103
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pohan Kung, Ying-Jing Lu, Chi-Cheng Hung, Yu-Sheng Wang, Shiu-Ko Jangjian
  • Patent number: 11165276
    Abstract: A adapter having an inputting terminal and an outputting terminal is provided. The adapter further includes a converter having a first side and a second side, a testing switch having a first terminal and a second terminal, a detecting circuit and a first indicator. The first side is coupled to the inputting terminal. The second side is coupled to the outputting terminal. The converter is used to convert inputting power for providing outputting power to a load system. The first terminal is coupled to the second side. The detecting circuit is coupled to the second terminal. When the first terminal and the second terminal of the testing switch are conducted, the load system is disconnected with the adapter by the detecting circuit. The detecting circuit is used to detect an outputting signal for generating a detecting result. The first indicator sends a message according to the detecting result.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 2, 2021
    Assignee: CYBER POWER SYSTEMS, INC.
    Inventors: Yu-Sheng Wang, Hong-Lun Wang, Cheng-Yang Su
  • Publication number: 20210296450
    Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Ching-Hwanq Su
  • Publication number: 20210257254
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 19, 2021
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Patent number: 11043573
    Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chi-Cheng Hung, Yu-Sheng Wang, Weng-Cheng Chen, Hao-Han Wei, Ming-Ching Chung, Chi-Cherng Jeng
  • Patent number: 11031486
    Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Ching-Hwanq Su
  • Patent number: 10985061
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Publication number: 20210043521
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20210043772
    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
  • Publication number: 20210005743
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: POHAN KUNG, YING -JING LU, CHI-CHENG HUNG, YU-SHENG WANG, SHIU-KO JANGJIAN
  • Patent number: 10879629
    Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive:the suppressor additive:the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jun-Nan Nian, Jyun-Ru Wu, Shiu-Ko Jangjian, Yu-Ren Peng, Chi-Cheng Hung, Yu-Sheng Wang
  • Patent number: 10867845
    Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Ching-Hwanq Su, Liang-Yueh Ou Yang, Ming-Hsing Tsai, Yu-Ting Lin
  • Patent number: 10840184
    Abstract: In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is over the first portion. A second metal layer is deposited over the carbon-containing layer to fill a third portion of the second recess, which is over the second portion. A carbon concentration of the carbon-containing layer is greater than a carbon concentration of the first metal layer and a carbon concentration of the second metal layer, and the carbon concentration of the first metal layer is substantially the same as the carbon concentration of the second metal layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-Nan Nian, Shiu-Ko Jangjian, Chi-Cheng Hung, Yu-Sheng Wang, Hung-Hsu Chen
  • Patent number: 10840330
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10833196
    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su