Yu-Sheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.
Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive:the suppressor additive:the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.
November 30, 2018
Date of Patent:
December 29, 2020
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including at least a first metal; a conductive layer formed above the gate electrode, the conductive layer including an alloy layer, the alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extending from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure; and a contact feature disposed above the metal gate structure, wherein the contact feature is in direct contact with a top surface of the conductive layer.
Abstract: An organic light emitting diode (OLED) display panel includes a substrate, a reflective electrode disposed on the substrate, and a pixel define layer (PDL) formed on the substrate and the reflective electrode layer. The reflective electrode layer has multiple reflective structures, and each reflective structure has a first region and a second region. The PDL is provided with multiple openings corresponding to the reflective structures, such that the first region and the second region of each of the reflective structures are exposed in a corresponding one of the openings. Multiple organic emissive structures are correspondingly formed in the openings and covering the reflective structures, forming a plurality of pixels. For each respective pixel of the pixels, a first reflective ratio of the respective pixel corresponding to the first region is greater than a second reflective ratio of the respective pixel corresponding to the second region.
April 30, 2020
Date of Patent:
December 8, 2020
AU OPTRONICS CORPORATION
Yung-Sheng Ting, Yu-Ching Wang, Yi-Hui Lin
Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
Abstract: In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is over the first portion. A second metal layer is deposited over the carbon-containing layer to fill a third portion of the second recess, which is over the second portion. A carbon concentration of the carbon-containing layer is greater than a carbon concentration of the first metal layer and a carbon concentration of the second metal layer, and the carbon concentration of the first metal layer is substantially the same as the carbon concentration of the second metal layer.
Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
Abstract: A computer-implemented method for processing objects on touch screen devices is proposed. According to the method, one or more grid sizes is determined, wherein the one or more grid sizes comprise one or more text grid sizes. The one or more text grid sizes are determined by at least one of character, word, sentence, and section. Based on the one or more grid sizes, the one or more objects on the touch screen could be divided into one or more grids. The objects on the screen could be selected discontinuously by selecting grids on the screen.
August 16, 2017
Date of Patent:
November 17, 2020
International Business Machines Corporation
Chun-Sheng Chung, Ping-Hung Lai, Yu-Chun Lin, Ting-Yi Wang
Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
Abstract: A method of distributing task regions for a plurality of cleaning devices, including: dividing a task map into a plurality of basic sub-regions according to concave corners corresponding to the shape of the task map; combining each two adjacent basic sub-regions, and calculating basic cleaning time corresponding to each of the combined basic sub-regions; repeatedly combining each two adjacent basic sub-regions according to the basic cleaning time, and obtaining a basic partition result; selecting starting blocks according to positions of the plurality of task sub-regions in the basic partitioning result; combining the task sub-regions according to the position of each starting block, the position of each task sub-region, and the cleaning time corresponding to each task sub-region, and obtaining the task region distribution result; enabling cleaning devices to perform cleaning tasks according to the position of each cleaning device and the task region distribution result.
Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.
Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.
Abstract: A method of distributing task areas, adapted to a cleaning device, is provided, including: receiving a task map; obtaining a shape that corresponds to the task map; dividing the task map into a plurality of sub-regions according to a plurality of recesses in the shape; merging the two adjacent sub-regions that have a common long side or short side, and obtaining a plurality of merge results that correspond to each of the merge actions; calculating a plurality of cleaning times for each of the merge results for the cleaning device; selecting the merge result that has the shortest cleaning times as a first distribution result; and enabling the cleaning device to perform a cleaning task according to the first distribution result.
Abstract: A display panel has a display area and a peripheral area. The peripheral area is located outside the display area. The display panel includes a first substrate, a second substrate, and a display medium layer. The second substrate is located above the first substrate and includes a first polarization layer, a first quarter wave plate (QWP), a reflection layer, and a pixel array. The first polarization layer is located within the display area and the peripheral area and includes a wire-grid polarizer. The first QWP is located within the peripheral area. The reflection layer is located within the peripheral area, in which the first QWP is located between the first polarization layer and the reflection layer. The pixel array is at least located within the display area. The display medium layer is located between the first substrate and the second substrate.
Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
Abstract: A positioning system includes a storage device, a lidar and a controller. The storage device stores a global map. The lidar generates an initial local map. The controller rotates the initial local map to generate a rotated local map, compares the rotated local map and the initial local map separately with a plurality of partial areas of the global map, so as to obtain at least one similar area, calculates at least one candidate coordinates for a mobile device on the global map according to the center point of each of the similar areas, and calculates similarity scores according to each of the candidate coordinates, and selects the candidate coordinates having highest similarity score for use as coordinate of the mobile device on the global map.
Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
Abstract: The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.
June 4, 2018
Date of Patent:
August 25, 2020
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Chi-Cheng Hung, Yu-Sheng Wang, Ting-Siang Su, Ching-Hwanq Su
Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.