Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.

Abstract: A method for setting an actual operation frequency of a memory is provided. The method includes the following steps. First, a memory model list is provided for selecting a memory model. Then, an estimation operation frequency of the memory is obtained according to the selected model. Finally, the operation frequency of a front side bus (FSB) is adjusted and cooperated with a frequency transformation ratio to generate the actual operation frequency of the memory according to the estimation operation frequency.

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer.

Abstract: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

Abstract: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

Abstract: A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.

Abstract: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

Abstract: This invention uses the pattern-based signal to accelerate the evaluation process as a means to replace complicated computing procedures. This invention is constructed through implementing absolute coordinates to produce pattern-based signals by position and two optical sensor signals, and through conducting the feature extraction process. This process produces feature signals of sidelong and overlapped issues. Furthermore, through transforming signals, feature signals can be handled by the digital data processor. Thus, this invention can achieve the three main objectives of wafer mapping.

Abstract: A needle-changing mechanism for use in a multiple-needle embroidery sewing machine is disclosed for controlling the changing of a selected sewing needle to a working position on the sewing platform of the sewing machine. The needle-changing mechanism includes a sensing plate having a gap portion sandwiched between two solid side portions. The position of the gap portion is changed by moving the sensing plate according to which needle is currently selected as the working needle. A plurality of photo detectors equal in number to the number of the needles of the sewing machine are arranged at equal intervals along a straight line relative to the axial orientation of the sensing plate such that the gap portion and the side portions of the sensing plate cause the photo detectors to output a pattern of positioning signals. A controller, which receives and processes output signals from the photo detectors, is used to control the movement of the needles so that the desired needle is positioned as the working needle.