Patents by Inventor Yu-Sheng Yi

Yu-Sheng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9025713
    Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 5, 2015
    Assignee: M31 Technology Corporation
    Inventors: Yu-Sheng Yi, Ting-Chun Huang, Yuan-Hsun Chang
  • Publication number: 20150098542
    Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: M31 Technology Corporation
    Inventors: Yu-Sheng Yi, Ting-Chun Huang, Yuan-Hsun Chang
  • Patent number: 8917133
    Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 23, 2014
    Assignee: M31 Technology Corporation
    Inventors: Chih-Jou Lin, Yuan-Hsun Chang, Cheng-Ji Chang, Ting-Chun Huang, Yu-Sheng Yi
  • Patent number: 8724762
    Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: May 13, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Yen-Yin Huang, Chauo-Min Chen, Kuan-Yu Chen, Yu-Sheng Yi, Ming-Shih Yu
  • Publication number: 20140043082
    Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: M31 Technology Corporation
    Inventors: Chih-Jou Lin, Yuan-Hsun Chang, Cheng-Ji Chang, Ting-Chun Huang, Yu-Sheng Yi
  • Publication number: 20130010909
    Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
    Type: Application
    Filed: July 4, 2011
    Publication date: January 10, 2013
    Inventors: Yen-Yin Huang, Chauo-Min Chen, Kuan-Yu Chen, Yu-Sheng Yi, Ming-Shih Yu