Abstract: Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.