Patents by Inventor Yu-Shin Ryu
Yu-Shin Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908916Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.Type: GrantFiled: April 30, 2021Date of Patent: February 20, 2024Assignee: SK hynix system ic Inc.Inventors: Soon Yeol Park, Yoon Hyung Kim, Yu Shin Ryu
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Patent number: 11158720Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region. A second insulation pattern is disposed over the second region of the semiconductor region. The second insulation pattern has a thickness greater than a thickness of the first insulation pattern. A gate electrode is disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.Type: GrantFiled: February 6, 2019Date of Patent: October 26, 2021Assignee: SK hynix system ic Inc.Inventors: Soon Yeol Park, Yoon Hyung Kim, Yu Shin Ryu
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Publication number: 20210257477Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.Type: ApplicationFiled: April 30, 2021Publication date: August 19, 2021Inventors: Soon Yeol PARK, Yoon Hyung KIM, Yu Shin RYU
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Patent number: 10978587Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.Type: GrantFiled: September 9, 2019Date of Patent: April 13, 2021Assignee: KEY FOUNDRY CO., LTD.Inventors: Yu Shin Ryu, Tae Hoon Lee, Bo Seok Oh
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Patent number: 10586863Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: GrantFiled: May 22, 2017Date of Patent: March 10, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
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Publication number: 20200020801Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.Type: ApplicationFiled: September 9, 2019Publication date: January 16, 2020Applicant: Magnachip Semiconductor, Ltd.Inventors: Yu Shin RYU, Tae Hoon LEE, Bo Seok OH
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Publication number: 20190378908Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.Type: ApplicationFiled: February 6, 2019Publication date: December 12, 2019Inventors: Soon Yeol PARK, Yoon Hyung KIM, Yu Shin RYU
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Patent number: 10468522Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.Type: GrantFiled: May 26, 2017Date of Patent: November 5, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Yu Shin Ryu, Tae Hoon Lee, Bo Seok Oh
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Patent number: 10381460Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.Type: GrantFiled: January 27, 2017Date of Patent: August 13, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Yu Shin Ryu, Bo Seok Oh, Jin Yeong Son
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Publication number: 20170263762Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: ApplicationFiled: May 22, 2017Publication date: September 14, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: Francois HEBERT, Yon Sup PANG, Yu Shin RYU, Seong Min CHO, Ju Ho KIM
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Publication number: 20170263763Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: Yu Shin RYU, Tae Hoon LEE, Bo Seok OH
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Patent number: 9698258Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.Type: GrantFiled: July 17, 2015Date of Patent: July 4, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Yu Shin Ryu, Tae Hoon Lee, Bo Seok Oh
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Patent number: 9691893Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: GrantFiled: October 20, 2014Date of Patent: June 27, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
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Publication number: 20170141213Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Applicant: MagnaChip Semiconductor, Ltd.Inventors: Yu Shin RYU, Bo Seok OH, Jin Yeong SON
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Patent number: 9595590Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.Type: GrantFiled: March 31, 2014Date of Patent: March 14, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Yu Shin Ryu, Bo Seok Oh
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Publication number: 20160181419Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.Type: ApplicationFiled: July 17, 2015Publication date: June 23, 2016Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Yu Shin RYU, Tae Hoon LEE, Bo Seok OH
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Patent number: 9299919Abstract: A Hall sensor with improved doping profile is disclosed. The Hall sensor includes a semiconductor substrate, a sensing region formed on the substrate, an isolation region formed on the sensing region, and a high concentration doping region formed on an upper portion of the sensing region.Type: GrantFiled: February 19, 2015Date of Patent: March 29, 2016Assignee: Magnachip Semiconductor, Ltd.Inventors: Seong Woo Lee, Jae Hyung Jang, Hee Baeg An, Yu Shin Ryu
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Publication number: 20150255595Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.Type: ApplicationFiled: October 20, 2014Publication date: September 10, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Francois HEBERT, Yon Sup PANG, Yu Shin RYU, Seong Min CHO, Ju Ho KIM
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Publication number: 20150102405Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.Type: ApplicationFiled: March 31, 2014Publication date: April 16, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Yu Shin RYU, Bo Seok OH
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Patent number: 8243419Abstract: A capacitor structure includes: a first electrode configured to include a plurality of openings; a second electrode formed in each center of the openings; and a dielectric layer formed to surround the second electrode and fill the openings of the first electrode.Type: GrantFiled: October 1, 2009Date of Patent: August 14, 2012Assignee: MagnaChip Semiconductor, Ltd.Inventor: Yu-Shin Ryu