Patents by Inventor Yu-Shu Cheng

Yu-Shu Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154314
    Abstract: An antenna device includes a substrate, two T-shaped radiation portions, two feeding portions and an isolation structure. The substrate has an upper surface, a side surface and a lower surface. Two opposite ends of the side surface are connected to the upper surface and the lower surface, respectively. The two T-shaped radiation portions are located on the upper surface of the substrate. The two feeding portions are connected to the two T-shaped radiation portions, respectively, and the two feeding portions are located on the side surface of the substrate. The isolation structure is located on the upper surface of the substrate, and the isolation structure is disposed between the two T-shaped radiation portions.
    Type: Application
    Filed: March 1, 2023
    Publication date: May 9, 2024
    Inventors: Hsin-Hung Lin, Yu Shu Tai, WEI-CHEN CHENG
  • Publication number: 20240097351
    Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 21, 2024
    Inventors: Hsin Hung LIN, Yu Shu TAI, Wei Chen CHENG
  • Patent number: 11785769
    Abstract: A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.
    Type: Grant
    Filed: July 3, 2022
    Date of Patent: October 10, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Yao-Ting Tsai
  • Publication number: 20220336481
    Abstract: A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.
    Type: Application
    Filed: July 3, 2022
    Publication date: October 20, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Yao-Ting Tsai
  • Patent number: 11424254
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 23, 2022
    Assignee: WInbond Electronics Corp.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Yao-Ting Tsai
  • Patent number: 11398383
    Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 26, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Chun-Sheng Lu
  • Publication number: 20210398813
    Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Inventors: Hsin-Huang SHEN, Yu-Shu CHENG, Chun-Sheng LU
  • Publication number: 20210183874
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Yao-Ting Tsai