Patents by Inventor Yu-Shu Lin
Yu-Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12406860Abstract: A method of forming a conductive layer of a semiconductor device is described. The method includes forming a hard mask layer on a metal layer overlying a substrate, in which the metal layer includes tungsten. The method further includes patterning the hard mask layer until portions of the metal layer are exposed from the patterned hard mask layer. The method further includes performing a plasma process to the metal layer through the patterned hard mask layer until portions of the substrate are exposed from the etched metal layer, in which a process gas mixture used in the plasma process includes a fluorine based gas, a chlorine based gas, and oxygen.Type: GrantFiled: July 27, 2022Date of Patent: September 2, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yu Shu Lin
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Publication number: 20250241038Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: ApplicationFiled: April 8, 2025Publication date: July 24, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20250169119Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: ApplicationFiled: January 16, 2025Publication date: May 22, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Patent number: 12300743Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: GrantFiled: May 16, 2024Date of Patent: May 13, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 12237415Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: GrantFiled: August 17, 2023Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Publication number: 20240304705Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: ApplicationFiled: May 16, 2024Publication date: September 12, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Publication number: 20240266437Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.Type: ApplicationFiled: April 15, 2024Publication date: August 8, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
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Patent number: 12021134Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.Type: GrantFiled: December 1, 2022Date of Patent: June 25, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 11990547Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.Type: GrantFiled: September 27, 2020Date of Patent: May 21, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
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Publication number: 20240038545Abstract: A method of forming a conductive layer of a semiconductor device is described. The method includes forming a hard mask layer on a metal layer overlying a substrate, in which the metal layer includes tungsten. The method further includes patterning the hard mask layer until portions of the metal layer are exposed from the patterned hard mask layer. The method further includes performing a plasma process to the metal layer through the patterned hard mask layer until portions of the substrate are exposed from the etched metal layer, in which a process gas mixture used in the plasma process includes a fluorine based gas, a chlorine based gas, and oxygen.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventor: Yu Shu LIN
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Publication number: 20230395719Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Patent number: 11769833Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: GrantFiled: September 30, 2022Date of Patent: September 26, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Publication number: 20230097129Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: ApplicationFiled: December 1, 2022Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 11587835Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.Type: GrantFiled: June 3, 2021Date of Patent: February 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
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Publication number: 20230033820Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.Type: ApplicationFiled: September 30, 2022Publication date: February 2, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Patent number: 11545560Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.Type: GrantFiled: January 28, 2021Date of Patent: January 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
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Patent number: 11495686Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.Type: GrantFiled: January 13, 2021Date of Patent: November 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Publication number: 20220190160Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.Type: ApplicationFiled: January 13, 2021Publication date: June 16, 2022Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
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Publication number: 20220069127Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.Type: ApplicationFiled: September 27, 2020Publication date: March 3, 2022Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
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Publication number: 20210287944Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin