Patents by Inventor Yu-Shuen TANG
Yu-Shuen TANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10223334Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix multiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: July 20, 2017Date of Patent: March 5, 2019Assignee: NOVUMIND LIMITEDInventors: Chien-Ping Lu, Yu-Shuen Tang
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Patent number: 10216704Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix multiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: July 20, 2017Date of Patent: February 26, 2019Assignee: NOVUMIND LIMITEDInventors: Chien-Ping Lu, Yu-Shuen Tang
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Patent number: 10169298Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix multiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: May 11, 2017Date of Patent: January 1, 2019Assignee: NOVUMIND LIMITEDInventors: Chien-Ping Lu, Yu-Shuen Tang
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Patent number: 10073816Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix mutiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: July 20, 2017Date of Patent: September 11, 2018Assignee: NovuMind LimitedInventors: Chien-Ping Lu, Yu-Shuen Tang
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Publication number: 20140229795Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes a first ECC codec that selectively performs different error corrections with different parameters; means for providing a selected parameter to the ECC codec for initializing the ECC codec; and a second ECC codec that corrects the selected error-prone parameter in order to provide an error-free parameter to the first ECC codec.Type: ApplicationFiled: April 16, 2014Publication date: August 14, 2014Applicant: Skymedi CorporationInventors: Yu-Shuen TANG, Chuang Cheng
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Patent number: 8762813Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter.Type: GrantFiled: May 17, 2010Date of Patent: June 24, 2014Assignee: Skymedi CorporationInventors: Yu-Shuen Tang, Chuang Cheng
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Publication number: 20120233401Abstract: An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: SKYMEDI CORPORATIONInventors: Hsingho LIU, Fuja SHONE, Chuang CHENG, Yu-Shuen TANG
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Publication number: 20110283164Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter.Type: ApplicationFiled: May 17, 2010Publication date: November 17, 2011Applicant: SKYMEDI CORPORATIONInventors: Yu-Shuen TANG, CHUANG CHENG