Abstract: A clock generator includes a resistor-capacitor-based voltage-controlled oscillator (RC-based VCO) that generates an output signal with oscillation frequency controlled by an input voltage at an input node; and a temperature compensator that generates the input voltage to compensate change of the oscillation frequency associated with a change in temperature.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: A fabrication method for shallow trench isolation is provided. The method includes forming a pad oxide layer on a substrate, followed by forming a mask layer on the pad oxide layer. The mask layer is then patterned. Using the patterned mask as a mask, the pad oxide layer and the substrate are etched to form a trench in the substrate. A tilt-angled fluorine implantation is performed to form a substrate surface with fluorine ions around the top corner of the trench. A thermal oxidation process is further conducted on a surface of the trench to form a thicker liner oxide layer at the top corner of the trench. An insulation layer is then formed on the substrate, filling the trench. The insulation layer above the mask layer is removed followed by removing the mask layer and the pad oxide layer.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: An electrostatic discharge (ESD) protection circuit. A first NMOS transistor has a drain terminal connected to an I/O pad and a gate terminal connected to a voltage source. A second NMOS transistor has a drain terminal connected to a source terminal of the first NMOS transistor and a source and a gate terminal connected to a ground voltage. A third NMOS transistor has a source terminal connected to the I/O pad, a drain terminal connected to the voltage source and a gate and a substrate terminal connected to the ground voltage. A first PMOS transistor has a drain terminal connected to the ground voltage and a substrate terminal of the second NMOS transistor, a source and a substrate terminal connected to the I/O pad and a gate terminal connected to the voltage source. And, a second PMOS transistor has a source and a gate terminal connected to the voltage source, a drain terminal connected to the I/O pad and a substrate terminal connected to a drain terminal of the third NMOS transistor.