Abstract: A human antibody which comprises a complementarity determining region of an H chain consisting of the amino acid sequence as shown in SEQ ID NOs: 1 to 3 and a complementarity determining region of an L chain consisting of the amino acid sequence as shown in SEQ ID NOs: 4 to 6. The human antibody of the present invention has the activity to specifically bind to transthyretin (TTR) with structural change and the activity to inhibit fibrillization of TTR and is a human antibody suitable for application to human body.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A light emitting diode (LED) display apparatus includes first to third data lines, gate lines, a first color sub-pixel unit and second color sub-pixel units. The gate lines include (N?1)th, Nth and (N+1)th gate lines. The first color sub-pixel unit includes a first color LED electrically coupled to the first data line and the (N?1)th and Nth gate lines. When the (N?1)th or Nth gate line is enabled, the first color LED is turned on. The second color sub-pixel unit is electrically connected to the second data line, and includes a second color LED. The second color sub-pixel units are electrically coupled to the gate lines, respectively. When each gate line is enabled, the corresponding second color LED is turned on. A light emitting area of the first color sub-pixel unit is greater than a light emitting area of each second color sub-pixel unit.

Abstract: An apparatus and a method for are provided for a wireless power receiver.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A method and power transmitter for efficiently controlling power transmission to one or more power receivers in a wireless multi-power transmission system are provided. The method includes performing, when a predetermined measurement cycle arrives, a load measurement; comparing a current load measurement value with a previous load measurement value; determining whether the current load measurement value is increased over the previous load measurement value by at least as much as a first predetermined threshold; gradually increasing, when the load measurement value is increased over the previous load measurement value by at least as much as the first threshold, a transmission power value until a request for a subscription to a wireless multi-power transmission network from a power reception target within a predetermined time limit; and stopping, when the request for the subscription is not received before the time limit is exceeded, power transmission to the power reception target.

Abstract: A display device includes a plurality of sub-pixel arrays and each of sub-pixel arrays includes a plurality of first sub-pixels having a first color and forming a plurality of vertexes of a virtual quadrilateral, wherein there is not any other first sub-pixels having the first color located in the virtual quadrilateral; at least one second sub-pixel, having a second color different from the first color and located in the virtual quadrilateral; and at least one third sub-pixel, having a third color different from the first color and the second color and located in the virtual quadrilateral.

Abstract: A multiplexer is provided herein. The multiplexer has a plurality of first driving units and a plurality of second driving units. Each of the first driving units has a first data voltage input terminal, and each of the second driving units has a second data voltage input terminal. The first data voltage input terminal and the second data voltage input terminal are configured to receive pixel voltage signals with different polarities. In the first driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a first reset signal, wherein the transistor of the first driving unit is coupled to the first data voltage input terminal and a first data line. In the second driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a second reset signal, wherein the transistor of the second driving unit is coupled to the second data voltage input terminal and a second data line.

Abstract: Various embodiments of the present disclosure are directed towards a varactor comprising a reduced surface field (RESURF) region. In some embodiments, the varactor includes a drift region, a gate structure, a pair of contact regions, and a RESURF region. The drift region is within a substrate and has a first doping type. The gate structure overlies the drift region. The contact regions are within the substrate and overlie the drift region. Further, the contact regions have the first doping type. The gate structure is laterally sandwiched between the contact regions. The RESURF region is in the substrate, below the drift region, and has a second doping type. The second doping type is opposite the first doping type. The RESURF region aids in depleting the drift region under the gate structure, which decreases the minimum capacitance of the varactor and increases the tuning range of the varactor.

Abstract: A control circuit includes a switching circuit and a select circuit. The switching circuit is configured to receive a scan signal, a first switching signal, and a second switching signal, and output the first switching signal and the second switching signal according to the scan signal. The select circuit is configured to receive a first supply voltage, a second supply voltage, the first switching signal, and the second switching signal, and selectively output the first supply voltage or the second supply voltage to a target electrode according to the first switching signal and the second switching signal.

Abstract: A sub-pixel rendering data conversion apparatus including an inverse sub-pixel rendering circuit and a sub-pixel rendering circuit is provided. The inverse sub-pixel rendering circuit receives the first sub-pixel rendering data converted from the first true image data and converting the first sub-pixel rendering data to the second true image data, and the first sub-pixel rendering data includes data of the first sub-pixel rendering arrangement. The sub-pixel rendering circuit converts the second true image data to the second sub-pixel rendering data and outputs the second sub-pixel rendering data to a display panel, the second sub-pixel rendering data includes data of the second sub-pixel rendering arrangement, and the display panel includes a plurality of sub-pixels arranged in the manner of the second sub-pixel rendering arrangement.

Abstract: A sub-pixel rendering data conversion apparatus including an inverse sub-pixel rendering circuit and a sub-pixel rendering circuit is provided. The inverse sub-pixel rendering circuit receives the first sub-pixel rendering data converted from the first true image data and converting the first sub-pixel rendering data to the second true image data, and the first sub-pixel rendering data includes data of the first sub-pixel rendering arrangement. The sub-pixel rendering circuit converts the second true image data to the second sub-pixel rendering data and outputs the second sub-pixel rendering data to a display panel, the second sub-pixel rendering data includes data of the second sub-pixel rendering arrangement, and the display panel includes a plurality of sub-pixels arranged in the manner of the second sub-pixel rendering arrangement.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A display device comprising an active area and a surrounding area is provided. The active area includes a common electrode for receiving a common voltage. The surrounding area is located at a side of the active area, and the surrounding area includes a shielding metal layer and a surrounding circuit. The shielding metal layer is electrically isolated from the common electrode and receives a shielding voltage. The surrounding circuit and a first shielding metal are overlapped in a vertical projection direction, and the common voltage is power-isolated from the shielding voltage.

Abstract: A gate driving circuit includes a plurality of shift register circuits, where the shift register circuits are configured to drive a plurality of pixel rows. The gate driving circuit may be operated in a first mode and a second mode. When the gate driving circuit is operated in the first mode, the gate driving circuit is configured to drive, in a single frame, all pixel rows to be displayed. When the gate driving circuit is operated in the second mode, the gate driving circuit is configured to drive, in the single frame, some of the pixel rows to be displayed, and driven pixel rows of two adjacent frames are different.

Abstract: A humanized antibody which comprises a complementarity determining region of an H chain consisting of the amino acid sequence as shown in SEQ ID NOs: 1 to 3 and a complementarity determining region of an L chain consisting of the amino acid sequence as shown in SEQ ID NOs: 4 to 6. The humanized antibody of the present invention has the activity to specifically bind to transthyretin (TTR) with structural change and the activity to inhibit fibrillization of TTR and is a humanized antibody suitable for application to human body.

Abstract: A human antibody which comprises a complementarity determining region of an H chain consisting of the amino acid sequence as shown in SEQ ID NOs: 1 to 3 and a complementarity determining region of an L chain consisting of the amino acid sequence as shown in SEQ ID NOs: 4 to 6. The human antibody of the present invention has the activity to specifically bind to transthyretin (TTR) with structural change and the activity to inhibit fibrillization of TTR and is a human antibody suitable for application to human body.

Abstract: The light emitting diode display apparatus including a first substrate, a plurality of light emitting diodes, an adhesive layer, a color layer, and a second substrate is provided. The first substrate has a plurality of switching elements. The light emitting diode includes a first semiconductor layer, a plurality of second semiconductor layers, a plurality of light emitting layers, a first electrode, and a plurality of second electrodes. The first electrode is disposed on the first semiconductor layer. The second electrodes are respectively disposed on the corresponding second semiconductor layers. Each of the second electrodes is electrically connected to the corresponding switching element. The adhesive layer and the first substrate are respectively located at two opposite sides of the light emitting diode. The color layer is disposed on the first substrate and covers the adhesive layer and the light emitting diode. The second substrate is disposed opposite to the first substrate.

Abstract: A touch panel includes a substrate, scan lines, data lines, sub-pixels, a first conductive line, a second conductive line, and a conductive layer. The sub-pixels are arranged in columns along a first direction and arranged in rows along a second direction. Each of the sub-pixels includes an active element and a pixel electrode electrically connected with the active element. The active element is electrically connected with a corresponding scan line and a corresponding data line. The conductive layer overlaps the sub-pixels. The conductive layer includes a first electrode and a second electrode. The first electrode is electrically connected with the first conductive line. The second electrode is electrically connected with the second conductive line. The second electrode is separated from the first electrode. One of the first electrode and the second electrode is a touch electrode, and another one is a common electrode.

Abstract: An electronic device is provided. The electronic device includes a power receiver (PRx) that includes a receiver coil for receiving a power signal from a wireless power transmitting device and a wireless charging integrated circuit (IC) for converting the power signal into electrical energy, a power management circuit that is electrically connected to the PRx and configured to charge a battery using the electrical energy, and a processor that is electrically connected with the PRx and the power management circuit. The processor activates a power hold mode (PHM) if a charging level of the battery is a fully charged level and controls auxiliary charging of the battery.