Abstract: Various schemes for mitigating radio frequency (RF) interference are described, wherein an adaptive local oscillator (LO) is utilized. A receiver measures a jamming indicator which indicates a total power within a receiving band of the receiver. If the jamming indicator indicates a presence of substantial in-band interference, the receiver may program the LO to a different frequency and/or adjust a bandwidth of a filter accordingly to reject or reduce the interference. The receiver may adjust the LO and/or the filter repeatedly until the interference is rejected to a point that de-sense to the signal intended to be received is satisfactorily mitigated. The receiver may restore the LO and the filter to a default setting when the jamming indicator indicates that the interference is no longer present.

Abstract: Various schemes for mitigating radio frequency (RF) interference are described, wherein an adaptive local oscillator (LO) is utilized. A receiver measures a jamming indicator which indicates a total power within a receiving band of the receiver. If the jamming indicator indicates a presence of substantial in-band interference, the receiver may program the LO to a different frequency and/or adjust a bandwidth of a filter accordingly to reject or reduce the interference. The receiver may adjust the LO and/or the filter repeatedly until the interference is rejected to a point that de-sense to the signal intended to be received is satisfactorily mitigated. The receiver may restore the LO and the filter to a default setting when the jamming indicator indicates that the interference is no longer present.

Abstract: The present invention provides a method for controlling the critical dimension of a mask in dual damascene process. The method comprises providing a semiconductor structure which has a contact pattern thereon. A dielectric layer, such as a spin-on glass layer, is formed on the semiconductor structure and the contact pattern. Then a photoresist layer is formed on the dielectric layer. Next, the photoresist layer and the dielectric layer are etched to expose partial the semiconductor structure. Then the exposed semiconductor structure is removed followed by removing the total photoresist layer and the total dielectric layer.

Abstract: A method of gap filling is provided. A substrate comprising conductive structures thereon is provided. A gap is between the conductive structures. A conformal first dielectric layer is formed on the substrate and is used to protect the conductive structures and the substrate. An implanting process is performed with a high angle to implant impurities into the first dielectric layer. A second dielectric layer is formed on the implanted first dielectric layer to fully fill the gap.

Abstract: A method of improving gap filling of dielectric layer by implantation is disclosed. When a plurality of semiconductor structures are formed on a semiconductor substrate, there are gaps between portions of the semiconductor structure. First, a dielectric layer is formed over the surface of the semiconductor structure and then an implantation process is employed to implant ions as BF2+, B3+ and F− into first dielectric layer and more particularly into part of the first dielectric layer that corresponds to sidewall of semiconductor structure. Afterwards, rapid thermal process is employed to form SiOF molecules and B2O5 molecules on the first dielectric layer, and then a second dielectric layer is formed over the first dielectric layer. Because SiOF molecules improve step coverage of the second dielectric layer formation and B2O5 molecules enhance fluidity of second dielectric layer during formation of the second dielectric layer.

Abstract: An improved method of forming an inter-metal dielectric layer on a semiconductor substrate is described. A plurality of conductive lines is formed on the substrate wherein an gap is simultaneously formed between every two conductive lines to expose a part of the substrate. A conformal first dielectric layer is formed on the plurality of conductive lines and the exposed substrate. A spin-coating material layer is formed in the gap wherein the first dielectric layer on top of the plurality of conductive lines is exposed. A plasma treatment is performed on the exposed first dielectric layer. The remaining spin-coating material layer is removed until the first dielectric layer is exposed. A second dielectric layer is formed over the first dielectric layer.

Abstract: A method for forming wiring structures in integrated circuit devices is disclosed. The method, in one embodiment, firstly providing a substrate is carried out. Then an interlayer dielectric layer is formed over the substrate. Sequentially an etching stop layer is formed and wherein the etching stop layer is patterned. Thus formation of a dielectric layer over the etching stop is achieved. Also photoresist mask is formed and defined. Therefore an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etching stop layer therein. Consequentially removing the photoresist mask and then depositing a first conductive metal layer are all carried out. Again, photoresist mask is formed and defined. The next step is removing excess parts of the conductive metal. Sequentially the step is depositing a second conductive metal layer. Finally the surface of integrated circuit device is planarized herein.

Abstract: The present method provides a method for preparing the PI varnish which has the steps of: 1) preparing a mixed solution of 60-100% by weight aprotic solvent, and 0-40% by weight aromatic solvent; 2) adding into the mixed solution in a mole ratio of 1:9 two aromatic diamines; and 3) further adding in the mixed solution in a mole ratio of 1:5 two aromatic dianhydrides. Such PI has a suitable thermal expansion coefficient and characteristics different form those of the PI currently in use.

Abstract: A method of manufacturing a flexible amorphous silicon solar cell includes the steps of: a) coating a PI varnish on a glass substrate; b) imidizing the PI varnish film; c) vacuum-depositing a metal film on the PI film; d) vacuum-depositing an amorphous silicon film on the metal film; e) vacuum-depositing a transparent conducting film on the amorphous silicon film; and f) separating the PI film from the glass substrate. The method also provides for preparing the PI varnish by the steps of: 1) preparing a mixed solution of 60-100% by weight aprotic solvent, and 0-40% by weight aromatic solvent; 2) adding into the mixed solution in a mole ratio of 1:9 two aromatic diamines; and 3) further adding in the mixed solution in a mole ratio of 1:5 two aromatic dianhydrides.