Abstract: A packet processing apparatus includes a memory configured to store, for each time slot number, switching information for switching output of a packet of each packet type, a counter configured to count the time slot number, an output control circuit configured to control the output, based on the switching information that corresponds to the time slot number currently counted, a transmitter configured to transmit a control packet for resetting the time slot number currently counted in each packet processing apparatus in a set path, in a predetermined direction of the set path in accordance with a predetermined timing, and a reset circuit configured to, in response to a start of a transmission of the control packet, reset the time slot number currently counted and restart a count operation of the counter.