Patents by Inventor Yu-Te Chen

Yu-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Publication number: 20240113225
    Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Wei Tsai, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240113187
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
  • Publication number: 20240113222
    Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.
    Type: Application
    Filed: January 3, 2023
    Publication date: April 4, 2024
    Inventors: Yan-Yi Chen, Wu-Wei Tsai, Yu-Ming Hsiang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11940645
    Abstract: A front light module includes a reflective display device, a front light guide, and a light emitting unit plate. The front light guide plate includes a micro-structure. The micro-structure has a first angle between a surface thereof close to the light emitting unit and an upper surface of the front light guide plate. The micro-structure has a second angle between a surface thereof away from the light emitting unit and the upper surface of the front light guide plate. The micro-structure has a third angle between the surface thereof close to the light emitting unit and the surface thereof away from the light emitting unit. The first angle is within a range between 30 degrees and 60 degrees, the second angle is within a range between 30 degrees and 59 degrees, and the third angle is greater than 90 degrees.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: March 26, 2024
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Chun-Te Wang, Yu-Shan Shen, Yen-Lung Chen
  • Publication number: 20240096712
    Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Chieh-Fang Chen, Yen-Chung Ho, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 11924964
    Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 5, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lin Hui Chen, Songtao Lu, Chien Te Chen, Yu Ying Tan, Huang Pao Yi, Ching Chuan Hsieh, T. Sharanya Kaminda, Chia-Hsuan Huang
  • Patent number: 11916155
    Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
  • Patent number: 11607023
    Abstract: A hair dryer comprises a fan, a heater, a temperature sensor, and a controller. The heater is disposed at the airflow output end of the fan and used to heat the airflow output by the fan. The temperature sensor is pointed to the hair, receiving the infrared light radiated by the hair to obtain the temperature of the hair, determining the dryness of the hair according to at least one of the temperature of the hair and the rate of temperature variation of the hair, and outputting a corresponding control signal. The controller is electrically connected with the fan, the heater and the temperature sensor, and controlling at least one of the rotation speed of the fan and the heating power of the heater according to the control signal. The above-mentioned hair dryer not only can prevent from hair overheating and hair damage but also can shorten the time for drying hair.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 21, 2023
    Assignee: ORIENTAL SYSTEM TECHNOLOGY INC.
    Inventors: Teng-Wen Chang, Yu-Te Chen, Po-Tzu Chen, Yi-Chou Huang
  • Publication number: 20210153620
    Abstract: A hair dryer comprises a fan, a heater, a temperature sensor, and a controller. The heater is disposed at the airflow output end of the fan and used to heat the airflow output by the fan. The temperature sensor is pointed to the hair, receiving the infrared light radiated by the hair to obtain the temperature of the hair, determining the dryness of the hair according to at least one of the temperature of the hair and the rate of temperature variation of the hair, and outputting a corresponding control signal. The controller is electrically connected with the fan, the heater and the temperature sensor, and controlling at least one of the rotation speed of the fan and the heating power of the heater according to the control signal. The above-mentioned hair dryer not only can prevent from hair overheating and hair damage but also can shorten the time for drying hair.
    Type: Application
    Filed: December 24, 2019
    Publication date: May 27, 2021
    Inventors: TENG-WEN CHANG, YU-TE CHEN, PO-TZU CHEN, YI-CHOU HUANG
  • Patent number: 9711358
    Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Te Chen, En-Chiuan Liou, Chia-Hsun Tseng, Shin-Feng Su, Yu-Ting Hung, Meng-Lin Tsai
  • Publication number: 20170117149
    Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 27, 2017
    Inventors: Yu-Te Chen, En-Chiuan Liou, Chia-Hsun Tseng, Shin-Feng Su, Yu-Ting Hung, Meng-Lin Tsai
  • Patent number: 9583343
    Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Te Chen, En-Chiuan Liou, Chia-Hsun Tseng, Shin-Feng Su, Yu-Ting Hung, Meng-Lin Tsai
  • Publication number: 20170025286
    Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.
    Type: Application
    Filed: July 26, 2015
    Publication date: January 26, 2017
    Inventors: Yu-Te Chen, Chia-Hsun Tseng, En-Chiuan Liou, Chiung-Lin Hsu, Meng-Lin Tsai, Jan-Fu Yang, Yu-Ting Hung, Shin-Feng Su
  • Patent number: 9548216
    Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.
    Type: Grant
    Filed: July 26, 2015
    Date of Patent: January 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Te Chen, Chia-Hsun Tseng, En-Chiuan Liou, Chiung-Lin Hsu, Meng-Lin Tsai, Jan-Fu Yang, Yu-Ting Hung, Shin-Feng Su
  • Publication number: 20160343567
    Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.
    Type: Application
    Filed: June 29, 2015
    Publication date: November 24, 2016
    Inventors: Yu-Te Chen, En-Chiuan Liou, Chia-Hsun Tseng, Shin-Feng Su, Yu-Ting Hung, Meng-Lin Tsai
  • Patent number: 9313222
    Abstract: A method, an electronic device, and a user interface for on-demand detecting a malware are provided and adapted for estimating whether an application has vulnerabilities or malicious behaviors. The method includes the following steps. Firstly, evaluating a risk level and a test time of the application which has vulnerabilities or malicious behaviors. Next, detecting the application by selection of user to estimate the risk level of the application which has vulnerabilities or malicious behaviors and then correspondingly generating a detection result. Therefore, the method, the electronic device, and the user interface for on-demand detecting the malware can detect the risk level of the application which has vulnerabilities or malicious behaviors before getting virus pattern of the variant or new malware.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 12, 2016
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Pei-Wen Huang, Hsiang-An Wen, Ching-Hao Mao, Yu-Te Chen, Pei Te Chen
  • Publication number: 20150319187
    Abstract: A method, an electronic device, and a user interface for on-demand detecting a malware are provided and adapted for estimating whether an application has vulnerabilities or malicious behaviors. The method includes the following steps. Firstly, evaluating a risk level and a test time of the application which has vulnerabilities or malicious behaviors. Next, detecting the application by selection of user to estimate the risk level of the application which has vulnerabilities or malicious behaviors and then correspondingly generating a detection result. Therefore, the method, the electronic device, and the user interface for on-demand detecting the malware can detect the risk level of the application which has vulnerabilities or malicious behaviors before getting virus pattern of the variant or new malware.
    Type: Application
    Filed: June 27, 2014
    Publication date: November 5, 2015
    Inventors: PEI-WEN HUANG, HSIANG-AN WEN, CHING-HAO MAO, YU-TE CHEN, PEI TE CHEN
  • Patent number: 8035794
    Abstract: A double-layer liquid crystal lens comprises a first transparent substrate, a second transparent substrate, a third transparent substrate, a first liquid crystal layer interposed between the first and the second transparent substrates, and a second liquid crystal layer interposed between the second and the third transparent substrates. The upper side of the first transparent substrate is provided with a transparent ITO electrode and an alignment film disposed on the transparent electrode. Each of the upper and the lower sides of the second transparent substrate is provided with a alignment film. The upper side of the third transparent substrate is provided with an apertured electrode while the lower side thereof is provided with an alignment film. The first and the third transparent substrates are made of glass while the second transparent substrate is made of plastic material.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 11, 2011
    Assignee: United Radiant Technology Corporation
    Inventors: Ching-Yuan Ju, Zhi-Long Luo, Chi-Hung Lin, Yu-Te Chen
  • Publication number: 20110245604
    Abstract: The present invention provides a capsule endoscope and a capsule endoscopy system. The capsule endoscope includes a power supply module, an image function module and a power control module. The image function module is configured to capture the image outside the capsule endoscope. The power control module is electrically connected to the power supply module and includes an electronic switch. The power control module controls the electronic switch according to a predetermined condition to control the electric power provided from the power supply module to the image function module. By this configuration, the power control module is able to suspend the power supply until the capsule endoscope reaches the specific location in the digestive tract, and then starts the power supplying to enable the successive image inspection of the capsule endoscope. Therefore, the electric power is conserved to enable the inspection of the end portion of digestive system of the capsule endoscope.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Inventors: CHUEN-TAI YEH, Tah-Yeong Lin, Chia-Sung Wu, Yu-Te Chen